/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 QLogic Corporation. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _QL_NX_H
#define _QL_NX_H
/*
* ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
*
* ***********************************************************************
* * **
* * NOTICE **
* * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
* * ALL RIGHTS RESERVED **
* * **
* ***********************************************************************
*
*/
#ifdef __cplusplus
extern "C" {
#endif
/*
* Following are the states of the Phantom. Phantom will set them and
* Host will read to check if the fields are correct.
*/
/* Host writes the following to notify that it has done the init-handshake */
/* CRB_RELATED */
/* Every driver should use these Device State */
/* used for ethtool tests */
/* 12 registers to store MAC addresses for 8 PCI functions */
/* ends here */
/*
* WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an
* ILLEGAL hub!!!!!
*/
/* Hub 0 */
/* Hub 1 */
/* Hub 2 */
/* Hub 3 */
/* Hub 4 */
/* Hub 5 */
/* Hub 6 */
/* This field defines PCI/X adr [25:20] of agents on the CRB */
#define UNM_HW_PX_MAP_CRB_PH 0
/*
* #define PX_MAP_CRB_SS 41
*/
/* This field defines CRB adr [31:20] of the agents */
/*
* ROM USB CRB space is divided into 4 regions depending on decode of
* address bits [19:16]
*/
/* ROMUSB GLB register definitions */
/* Lock IDs for ROM lock */
/* Lock IDs for PHY lock */
/* HACK upon HACK upon HACK (for PCIE builds) */
/* window 1 pcie slot */
/*
* ====================== BASE ADDRESSES ON-CHIP ======================
* Base addresses of major components on-chip.
* ====================== BASE ADDRESSES ON-CHIP ======================
*/
/*
* Imbus address bit used to indicate a host address. This bit is
* eliminated by the pcie bar and bar select before presentation
* over pcie.
*/
/* host memory via IMBUS */
/*
* The ifdef at the bottom should go. All drivers should start using the above
* 2 defines.
*/
#ifdef P3
#else
#endif
/*
* h/w block.
*/
/*
* Configuration registers.
*/
/*
* Register offsets for MN
*/
/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
/* ====================== Configuration Constants ======================== */
(speed <= MAX_CORE_CLK_SPEED))
(ticks <= P2_MAX_TICKS_PER_SEC))
/* CAM RAM */
#define UNM_PORT_MODE_NONE 0
/*
* Following define address space withing PCIX CRB space to talk with
* devices on the storage side PCI bus.
*/
/*
* Configuration registers. These are the same offsets on both host and
* storage side PCI blocks.
*/
/*
*/
/*
* Configuration registers.
*/
#ifdef PCIX
#else
#endif
/*
* The PCI VendorID and DeviceID for our board.
*/
/* ISP 3031 related declarations */
typedef struct {
typedef struct {
struct crb_addr_pair {
};
/*
* ************************************************************************
* PCI related defines.
* ************************************************************************
*/
/*
* Interrupt related defines.
*/
/*
* Message Signaled Interrupts
*/
/*
*
*/
/*
* Interrupt state machine and other bits.
*/
/*
* PCI Interrupt Vector Values.
*/
#define NX_LEGACY_INTR_CONFIG \
{ \
{ \
.pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
\
{ \
\
{ \
\
{ \
\
{ \
\
{ \
\
{ \
\
{ \
}
/* Magic number to let user know flash is programmed */
/* 64K? */
#define UNM_PCI_MN_2M (0)
/* CRB window related */
((off) & 0xf0000))
/* #define ADDR_ERROR ((unsigned long ) 0xffffffff) */
/* PCI Windowing for DDR regions. */
/*
* IDC parameters are defined in �user area� in the flash
*/
/*
* Global Data in ql_nx.c source file.
*/
/*
* Global Function Prototypes in ql_nx.c source file.
*/
void ql_8021_reset_chip(ql_adapter_state_t *);
int ql_8021_load_risc(ql_adapter_state_t *);
void ql_8021_clr_hw_intr(ql_adapter_state_t *);
void ql_8021_clr_fw_intr(ql_adapter_state_t *);
void ql_8021_enable_intrs(ql_adapter_state_t *);
void ql_8021_disable_intrs(ql_adapter_state_t *);
void ql_8021_set_drv_active(ql_adapter_state_t *);
void ql_8021_clr_drv_active(ql_adapter_state_t *);
#ifdef __cplusplus
}
#endif
#endif /* _QL_NX_H */