emlxs_queue.h revision a9800beb32c1006bb21c8da39e0180ea440b7bad
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Emulex. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _EMLXS_QUEUE_H
#define _EMLXS_QUEUE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Queue entry defines */
/* EQ entries */
typedef struct EQE
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} EQE_t;
typedef union
{
} EQE_u;
/* CQ entries */
typedef struct CQE_CmplWQ
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_CmplWQ_t;
typedef struct CQE_RelWQ
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_RelWQ_t;
typedef struct CQE_UnsolRcv
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Status defines */
#define RQ_STATUS_SUCCESS 0x10
#define RQ_STATUS_BUFLEN_EXCEEDED 0x11
#define RQ_STATUS_NEED_BUFFER 0x12
#define RQ_STATUS_FRAME_DISCARDED 0x13
typedef struct CQE_XRI_Abort
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Defines for CQE Codes */
#define CQE_TYPE_WQ_COMPLETION 1
#define CQE_TYPE_RELEASE_WQE 2
#define CQE_TYPE_UNSOL_RCV 4
#define CQE_TYPE_XRI_ABORTED 5
typedef struct CQE_ASYNC_FCOE
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_ASYNC_LINK_STATE
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_ASYNC_GRP_5_QOS
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_ASYNC
{
/* Words 0-2 */
union
{
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_ASYNC_t;
/* port_speed defines */
#define PHY_1GHZ_LINK 3
#define PHY_10GHZ_LINK 4
/* event_code defines */
#define ASYNC_EVENT_CODE_LINK_STATE 1
#define ASYNC_EVENT_CODE_FCOE_FIP 2
#define ASYNC_EVENT_CODE_DCBX 3
#define ASYNC_EVENT_CODE_GRP_5 5
/* LINK_STATE - link_status defines */
#define ASYNC_EVENT_PHYS_LINK_DOWN 0
#define ASYNC_EVENT_PHYS_LINK_UP 1
#define ASYNC_EVENT_LOGICAL_LINK_DOWN 2
#define ASYNC_EVENT_LOGICAL_LINK_UP 3
/* FCOE_FIP - evt_type defines */
#define ASYNC_EVENT_NEW_FCF_DISC 1
#define ASYNC_EVENT_FCF_TABLE_FULL 2
#define ASYNC_EVENT_FCF_DEAD 3
#define ASYNC_EVENT_VIRT_LINK_CLEAR 4
#define ASYNC_EVENT_FCF_MODIFIED 5
/* GRP_5 - evt_type defines */
#define ASYNC_EVENT_QOS_SPEED 1
typedef struct CQE_MBOX
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_MBOX_t;
typedef union
{
/* Group 1 types */
/* Group 2 types */
} CQE_u;
/* RQ entries */
typedef struct RQE
{
} RQE_t;
/* Definitions for WQEs */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ELS_REQ_WQE;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ELS_RSP_WQE;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} GEN_REQ_WQE;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} XMIT_SEQ_WQE;
typedef struct
{
} FCP_WQE;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ABORT_WQE;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} BLS_WQE;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct emlxs_wqe
{
/* Words 0-5 */
union
{
} un;
#ifdef EMLXS_BIG_ENDIAN
/* Word 6 */
/* Word 7 */
/* Word 8 */
/* Word 9 */
/* Word 10 */
/* Word 11 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 6 */
/* Word 7 */
/* Word 8 */
/* Word 9 */
/* Word 10 */
/* Word 11 */
#endif
/* Words 12-15 */
} emlxs_wqe_t;
/* Defines for ContextType */
#define WQE_RPI_CONTEXT 0
#define WQE_VPI_CONTEXT 1
#define WQE_VFI_CONTEXT 2
#define WQE_FCFI_CONTEXT 3
/* Defines for CmdType */
#define WQE_TYPE_FCP_DATA_IN 0x00
#define WQE_TYPE_FCP_DATA_OUT 0x01
#define WQE_TYPE_ELS 0x0C
#define WQE_TYPE_GEN 0x08
#define WQE_TYPE_ABORT 0x08
#define WQE_TYPE_MASK_FIP 0x01
/* Defines for ELSId */
#define WQE_ELSID_FLOGI 0x03
#define WQE_ELSID_FDISC 0x02
#define WQE_ELSID_LOGO 0x01
#define WQE_ELSID_CMD 0x0
/* RQB */
#define RQB_HEADER_SIZE 32
#define RQB_DATA_SIZE 2048
#define RQB_COUNT 256
#define EMLXS_NUM_WQ_PAGES 4
#define EQ_DEPTH 1024
#define CQ_DEPTH 256
#define MQ_DEPTH 16
#define RQ_DEPTH_EXPONENT 9
/* Principal doorbell register layouts */
typedef struct emlxs_rqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_rqdb_t;
typedef union emlxs_rqdbu
{
typedef struct emlxs_wqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_wqdb_t;
typedef union emlxs_wqdbu
{
typedef struct emlxs_cqdb
{
#ifdef EMLXS_BIG_ENDIAN
/* 0 if processed entry is CQE */
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
/* 0 if processed entry is CQE */
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_cqdb_t;
typedef union emlxs_cqdbu
{
typedef struct emlxs_eqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_eqdb_t;
typedef union emlxs_eqdbu
{
typedef struct emlxs_mqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_mqdb_t;
typedef union emlxs_mqdbu
{
#ifdef __cplusplus
}
#endif
#endif /* _EMLXS_QUEUE_H */