/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2004-2012 Emulex. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _EMLXS_QUEUE_H
#define _EMLXS_QUEUE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Queue entry defines */
/* EQ entries */
typedef struct EQE
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} EQE_t;
typedef union
{
} EQE_u;
/* CQ entries */
typedef struct CQE_CmplWQ
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_CmplWQ_t;
typedef struct CQE_RelWQ
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_RelWQ_t;
typedef struct CQE_UnsolRcv
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_UnsolRcvV1
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Status defines */
typedef struct CQE_XRI_Abort
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Defines for CQE Codes */
typedef struct CQE_ASYNC_FCOE
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_ASYNC_LINK_STATE
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_ASYNC_GRP_5_QOS
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_ASYNC_FC_LINK_ATT
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct CQE_ASYNC_PORT
{
/* topology */
#define TOPOLOGY_UNKNOWN 0
/* att_type */
/* shared_link_status */
#define SHARED_STATUS_NONE 0
/* port_fault */
#define PORT_FAULT_NONE 0
typedef struct CQE_ASYNC
{
/* Words 0-2 */
union
{
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_ASYNC_t;
/* port_speed defines */
/* event_code defines */
/* FC Event */
/* LINK_STATE - link_status defines */
#define ASYNC_EVENT_PHYS_LINK_DOWN 0
/* FCOE_FIP - evt_type defines */
/* GRP_5 - evt_type defines */
/* PORT - evt_type defines */
typedef struct CQE_MBOX
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQE_MBOX_t;
typedef union
{
/* Group 1 types */
/* Group 2 types */
} CQE_u;
/* RQ entries */
typedef struct RQE
{
} RQE_t;
/* Definitions for WQEs */
typedef struct
{
/* Word 0 - 2 */
/* Word 3 */
#ifdef EMLXS_BIG_ENDIAN
/* Word 4 */
/* Word 5 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 4 */
/* Word 5 */
#endif
} ELS_REQ_WQE;
typedef struct
{
/* Word 0 - 2 */
/* Word 3 */
/* Word 4 */
#ifdef EMLXS_BIG_ENDIAN
/* Word 5 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 5 */
#endif
} ELS_RSP_WQE;
typedef struct
{
/* Word 0 - 2 */
/* Word 3 */
/* Word 4 */
#ifdef EMLXS_BIG_ENDIAN
/* Word 5 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 5 */
#endif
} GEN_REQ_WQE;
typedef struct
{
/* Word 0 - 2 */
/* Word 3 */
/* Word 4 */
#ifdef EMLXS_BIG_ENDIAN
/* Word 5 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 5 */
#endif
} XMIT_SEQ_WQE;
typedef struct
{
/* Word 0 - 2 */
/* Word 3 */
/* Word 4 */
/* Word 5 */
} FCP_WQE;
typedef struct
{
/* Word 0 - 2 */
#ifdef EMLXS_BIG_ENDIAN
/* Word 3 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 3 */
#endif
/* Word 4 - 5 */
} ABORT_WQE;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
/* Word 0 */
/* Word 1 */
/* Word 2 */
/* Word 3 */
/* Word 4 */
/* Word 5 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 0 */
/* Word 1 */
/* Word 2 */
/* Word 3 */
/* Word 4 */
/* Word 5 */
#endif
} BLS_WQE;
typedef struct
{
/* Word 0 - 4 */
#ifdef EMLXS_BIG_ENDIAN
/* Word 5 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 5 */
#endif
typedef struct emlxs_wqe
{
/* Words 0-5 */
union
{
} un;
#ifdef EMLXS_BIG_ENDIAN
/* Word 6 */
/* Word 7 */
/* Word 8 */
/* Word 9 */
/* Word 10 */
/* The following 16 bits may be */
/* overwritten by PHWQ */
/* Word 11 */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Word 6 */
/* Word 7 */
/* Word 8 */
/* Word 9 */
/* Word 10 */
/* The following 16 bits may be */
/* overwritten by PHWQ */
/* Word 11 */
#endif
/* Words 12 */
/* Words 13-15 */
} emlxs_wqe_t;
/* Used if PHWQ is enabled */
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Defines for ContextType */
#define WQE_RPI_CONTEXT 0
/* Defines for CmdType */
/* Defines for ELSId */
/* RQB */
/* Principal doorbell register layouts */
typedef struct emlxs_rqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_rqdb_t;
typedef union emlxs_rqdbu
{
typedef struct emlxs_wqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_wqdb_t;
typedef union emlxs_wqdbu
{
typedef struct emlxs_cqdb
{
#ifdef EMLXS_BIG_ENDIAN
/* 0 if processed entry is CQE */
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
/* 0 if processed entry is CQE */
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_cqdb_t;
typedef union emlxs_cqdbu
{
typedef struct emlxs_eqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_eqdb_t;
typedef union emlxs_eqdbu
{
typedef struct emlxs_mqdb
{
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} emlxs_mqdb_t;
typedef union emlxs_mqdbu
{
#ifdef __cplusplus
}
#endif
#endif /* _EMLXS_QUEUE_H */