emlxs_hw.h revision 93c20f2609342fd05f6625f16dfcb9348e7977f2
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Emulex. All rights reserved.
* Use is subject to License terms.
*/
#ifndef _EMLXS_HW_H
#define _EMLXS_HW_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef NPIV_SUPPORT
/* Maximum virtual ports per HBA (includes physical port) */
#define MAX_VPORTS 256
#define MAX_VPORTS_LIMITED 101
#else
/* Maximum virtual ports per HBA (includes physical port) */
#define MAX_VPORTS 1
#define MAX_VPORTS_LIMITED 1
#endif /* NPIV_SUPPORT */
/* Maximum transfer size per operation */
#define FC_MAX_TRANSFER 0x40000
#define PCB_SIZE 128
#define MBOX_SIZE 256
#define MBOX_EXTENSION_OFFSET MBOX_SIZE
#ifdef MBOX_EXT_SUPPORT
#define MBOX_EXTENSION_SIZE 1024
#else
#define MBOX_EXTENSION_SIZE 0
#endif /* MBOX_EXT_SUPPORT */
/* ------------------------------------------------------------------------- */
/* Total: 184 Cmd's + 184 Rsp's = 368 */
/* Command and response entry counts are not required to be equal */
#define SLIM_IOCB_CMD_ENTRIES \
#define SLIM_IOCB_RSP_ENTRIES \
#define SLIM_IOCB_ENTRIES \
/* SLI1 Definitions */
/* SLI2 Definitions */
#define SLI2_IOCB_CMD_SIZE 32
#define SLI2_IOCB_RSP_SIZE 32
#define SLI2_IOCB_MAX_SIZE \
#define SLI2_SLIM2_SIZE \
/* SLI3 Definitions */
#define SLI3_MAX_BDE 7
#define SLI3_IOCB_CMD_SIZE 128
#define SLI3_IOCB_RSP_SIZE 64
#define SLI3_IOCB_MAX_SIZE \
((SLI3_IOCB_CMD_SIZE * SLIM_IOCB_CMD_ENTRIES) + \
#define SLI3_SLIM2_SIZE \
#ifdef SLI3_SUPPORT
#define SLI_SLIM2_SIZE SLI3_SLIM2_SIZE
#define SLI_IOCB_MAX_SIZE SLI3_IOCB_MAX_SIZE
#else /* SLI2_SUPPORT */
#define SLI_SLIM2_SIZE SLI2_SLIM2_SIZE
#define SLI_IOCB_MAX_SIZE SLI2_IOCB_MAX_SIZE
#endif /* SLI3_SUPPORT */
#define FC_FCP_RING 0 /* use ring 0 for FCP initiator cmd */
#define FC_FCT_RING 0 /* use ring 0 for FCP target cmd */
/* max msg data in CMD_ADAPTER_MSG iocb */
#define MAX_MSG_DATA 28
/*
* Miscellaneous stuff....
*/
/* HBA Mgmt */
#define OWN_HOST 0 /* IOCB / Mailbox is owned by Host */
#define END_OF_CHAIN 0
/* defines for type field in fc header */
#define FC_ELS_DATA 0x01
#define FC_LLC_SNAP 0x05
#define FC_FCP_DATA 0x08
#define FC_CT_TYPE 0x20
#define EMLXS_MENLO_TYPE 0xFE
/* defines for rctl field in fc header */
#define FC_DEV_DATA 0x0
#define FC_UNSOL_CTL 0x2
#define FC_SOL_CTL 0x3
#define FC_UNSOL_DATA 0x4
#define FC_FCP_CMND 0x6
#define FC_ELS_REQ 0x22
#define FC_ELS_RSP 0x23
/*
* Common Transport structures and definitions
*
*/
#define EMLXS_COMMAND 0
#define EMLXS_RESPONSE 1
typedef union CtRevisionId {
/* Structure is in Big Endian format */
struct {
} bits;
typedef union CtCommandResponse {
/* Structure is in Big Endian format */
struct {
} bits;
typedef struct SliCtRequest {
/* Structure is in Big Endian format */
union {
struct gid {
} gid;
struct rft {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} rft;
struct rsnn {
char snn[256];
} rsnn;
struct rspn {
char spn[256];
} rspn;
} un;
typedef SliCtRequest_t SLI_CT_REQUEST;
#define SLI_CT_REVISION 1
/*
* FsType Definitions
*/
#define SLI_CT_MANAGEMENT_SERVICE 0xFA
#define SLI_CT_TIME_SERVICE 0xFB
#define SLI_CT_DIRECTORY_SERVICE 0xFC
#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
/*
* Directory Service Subtypes
*/
#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
/*
* Response Codes
*/
#define SLI_CT_RESPONSE_FS_RJT 0x8001
#define SLI_CT_RESPONSE_FS_ACC 0x8002
/*
* Reason Codes
*/
#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
#define SLI_CT_INVALID_COMMAND 0x01
#define SLI_CT_INVALID_VERSION 0x02
#define SLI_CT_LOGICAL_ERROR 0x03
#define SLI_CT_INVALID_IU_SIZE 0x04
#define SLI_CT_LOGICAL_BUSY 0x05
#define SLI_CT_PROTOCOL_ERROR 0x07
#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
#define SLI_CT_VENDOR_UNIQUE 0xff
/*
* Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
*/
#define SLI_CT_NO_PORT_ID 0x01
#define SLI_CT_NO_PORT_NAME 0x02
#define SLI_CT_NO_NODE_NAME 0x03
#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
#define SLI_CT_NO_IP_ADDRESS 0x05
#define SLI_CT_NO_IPA 0x06
#define SLI_CT_NO_FC4_TYPES 0x07
#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
#define SLI_CT_NO_PORT_TYPE 0x0A
#define SLI_CT_ACCESS_DENIED 0x10
#define SLI_CT_INVALID_PORT_ID 0x11
#define SLI_CT_DATABASE_EMPTY 0x12
#ifdef EMLXS_BIG_ENDIAN
#define CT_CMD_MASK 0xffff0000
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#define CT_CMD_MASK 0xffff
#endif
/*
* Management Server Interface Command Codes
*/
#define MS_GTIN 0x0100
#define MS_GIEL 0x0101
#define MS_GIET 0x0111
#define MS_GDID 0x0112
#define MS_GMID 0x0113
#define MS_GFN 0x0114
#define MS_GIELN 0x0115
#define MS_GMAL 0x0116
#define MS_GIEIL 0x0117
#define MS_GPL 0x0118
#define MS_GPT 0x0121
#define MS_GPPN 0x0122
#define MS_GAPNL 0x0124
#define MS_GPS 0x0126
#define MS_GPSC 0x0127
#define MS_GATIN 0x0128
#define MS_GSES 0x0130
#define MS_GPLNL 0x0191
#define MS_GPLT 0x0192
#define MS_GPLML 0x0193
#define MS_GPAB 0x0197
#define MS_GNPL 0x01A1
#define MS_GPNL 0x01A2
#define MS_GPFCP 0x01A4
#define MS_GPLI 0x01A5
#define MS_GNID 0x01B1
#define MS_RIELN 0x0215
#define MS_RPL 0x0280
#define MS_RPLN 0x0291
#define MS_RPLT 0x0292
#define MS_RPLM 0x0293
#define MS_RPAB 0x0298
#define MS_RPFCP 0x029A
#define MS_RPLI 0x029B
#define MS_DPL 0x0380
#define MS_DPLN 0x0391
#define MS_DPLM 0x0392
#define MS_DPLML 0x0393
#define MS_DPLI 0x0394
#define MS_DPAB 0x0395
#define MS_DPALL 0x039F
/*
* Name Server Command Codes
*/
#define SLI_CTNS_GA_NXT 0x0100
#define SLI_CTNS_GPN_ID 0x0112
#define SLI_CTNS_GNN_ID 0x0113
#define SLI_CTNS_GCS_ID 0x0114
#define SLI_CTNS_GFT_ID 0x0117
#define SLI_CTNS_GSPN_ID 0x0118
#define SLI_CTNS_GPT_ID 0x011A
#define SLI_CTNS_GID_PN 0x0121
#define SLI_CTNS_GID_NN 0x0131
#define SLI_CTNS_GIP_NN 0x0135
#define SLI_CTNS_GIPA_NN 0x0136
#define SLI_CTNS_GSNN_NN 0x0139
#define SLI_CTNS_GNN_IP 0x0153
#define SLI_CTNS_GIPA_IP 0x0156
#define SLI_CTNS_GID_FT 0x0171
#define SLI_CTNS_GID_PT 0x01A1
#define SLI_CTNS_RPN_ID 0x0212
#define SLI_CTNS_RNN_ID 0x0213
#define SLI_CTNS_RCS_ID 0x0214
#define SLI_CTNS_RFT_ID 0x0217
#define SLI_CTNS_RSPN_ID 0x0218
#define SLI_CTNS_RPT_ID 0x021A
#define SLI_CTNS_RIP_NN 0x0235
#define SLI_CTNS_RIPA_NN 0x0236
#define SLI_CTNS_RSNN_NN 0x0239
#define SLI_CTNS_DA_ID 0x0300
#define SLI_CT_LOOPBACK 0xFCFC
/*
* Port Types
*/
#define SLI_CTPT_N_PORT 0x01
#define SLI_CTPT_NL_PORT 0x02
#define SLI_CTPT_FNL_PORT 0x03
#define SLI_CTPT_IP 0x04
#define SLI_CTPT_FCP 0x08
#define SLI_CTPT_NX_PORT 0x7F
#define SLI_CTPT_F_PORT 0x81
#define SLI_CTPT_FL_PORT 0x82
#define SLI_CTPT_E_PORT 0x84
#define SLI_CT_LAST_ENTRY 0x80000000
/* ===================================================================== */
/*
* Start FireFly Register definitions
*/
/* PCI register offsets */
/* General PCI Register Definitions */
/* Refer To The PCI Specification For Detailed Explanations */
/* Register Offsets in little endian format */
#define PCI_SSID_REGISTER 0x2C
#define PCI_SSVID_REGISTER 0x2C
#define PCI_SSDID_REGISTER 0x2E
#define PCI_CAP_POINTER 0x34
/* PCIe adapters only */
/* Power management command states */
/* PCI access methods */
#define P_CONF_T1 1
#define P_CONF_T2 2
/* max number of pci buses */
#define MAX_PCI_BUSES 0xFF
/* number of PCI config bytes to access */
#define PCI_BYTE 1
#define PCI_WORD 2
#define PCI_DWORD 4
/* PCI related constants */
#define CMD_IO_ENBL 0x0001
#define CMD_MEM_ENBL 0x0002
#define CMD_BUS_MASTER 0x0004
#define CMD_MWI 0x0010
#define CMD_PARITY_CHK 0x0040
#define CMD_SERR_ENBL 0x0100
/* PCI addresses */
#define PCI_SPACE_ENABLE 0x0CF8
#define CF1_CONFIG_ADDR_REGISTER 0x0CF8
#define CF1_CONFIG_DATA_REGISTER 0x0CFC
#define CF2_FORWARD_REGISTER 0x0CFA
#define CF2_BASE_ADDRESS 0xC000
/*
* 0xF8 is a special value for FF11.1N6 firmware.
* Use 0x80 for pre-FF11.1N6 &N7, etc
*/
#define DEFAULT_PCI_LATENCY_CLOCKS 0xf8
#define PCI_LATENCY_VALUE 0xf8
/* ==== Register Bit Definitions ==== */
/* Used by SBUS adapter */
/* SBUS Control Register */
#define SBUS_CTRL_REG_OFFSET 0 /* Word offset from reg base addr */
/* Bit [6:4] IRL 1, lowset priority */
#define SBUS_CTRL_SIR_1 0x00000010
#define SBUS_CTRL_SIR_2 0x00000020
#define SBUS_CTRL_SIR_3 0x00000030
#define SBUS_CTRL_SIR_4 0x00000040
#define SBUS_CTRL_SIR_5 0x00000050
#define SBUS_CTRL_SIR_6 0x00000060
/* SBUS Status Register */
/* SBUS Update Register */
/* Host Attention Register */
#define HA_REG_OFFSET 0 /* Word offset from register base address */
#ifdef MSI_SUPPORT
/* Host attention interrupt map */
#define EMLXS_MSI_MAP8 \
#define EMLXS_MSI_MAP4 \
#define EMLXS_MSI_MAP2 {0, HA_R0ATT, 0, 0, 0, 0, 0, 0}
#define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0}
/* MSI 0 interrupt mask */
#define EMLXS_MSI0_MASK8 0
#define EMLXS_MSI0_MASK2 \
#define EMLXS_MSI0_MASK1 \
#define EMLXS_MSI_MAX_INTRS 8
#define EMLXS_MSI_MODE1 0
#define EMLXS_MSI_MODE2 1
#define EMLXS_MSI_MODE4 2
#define EMLXS_MSI_MODE8 3
#define EMLXS_MSI_MODES 4
#endif /* MSI_SUPPORT */
#define IO_THROTTLE_RESERVE 12
/* Chip Attention Register */
/* Host Status Register */
/* Host Control Register */
/* BIU Configuration Register */
/*
* End FireFly Register definitions
*/
/* ===================================================================== */
/*
* Start of FCP specific structures
*/
typedef struct emlxs_fcp_rsp {
#define SCSI_STAT_GOOD 0x00
#define SCSI_STAT_CHECK_COND 0x02
#define SCSI_STAT_COND_MET 0x04
#define SCSI_STAT_BUSY 0x08
#define SCSI_STAT_INTERMED 0x10
#define SCSI_STAT_INTERMED_CM 0x14
#define SCSI_STAT_RES_CNFLCT 0x18
#define SCSI_STAT_CMD_TERM 0x22
#define SCSI_STAT_QUE_FULL 0x28
#define SCSI_STAT_ACA_ACTIVE 0x30
#define SCSI_STAT_TASK_ABORT 0x40
/* Received in Big Endian format */
/* Received in Big Endian format */
/* Received in Big Endian format */
#define RSP_NO_FAILURE 0x00
#define RSP_DATA_BURST_ERR 0x01
#define RSP_CMD_FIELD_ERR 0x02
#define RSP_RO_MISMATCH_ERR 0x03
/*
* Define maximum size of SCSI Sense buffer. Seagate never issues
* more than 18 bytes of Sense data
*/
#define MAX_FCP_SNS 128
typedef emlxs_fcp_rsp FCP_RSP;
typedef struct emlxs_fcp_cmd {
/*
* # of bits to shift lun id to end up in right payload word, little
* endian = 8, big = 16.
*/
#ifdef EMLXS_LITTLE_ENDIAN
#define FC_LUN_SHIFT 8
#define FC_ADDR_MODE_SHIFT 0
#endif
#ifdef EMLXS_BIG_ENDIAN
#define FC_LUN_SHIFT 16
#define FC_ADDR_MODE_SHIFT 24
#endif
#define SIMPLE_Q 0x00
#define HEAD_OF_Q 0x01
#define ORDERED_Q 0x02
#define ACA_Q 0x04
#define UNTAGGED 0x05
typedef emlxs_fcp_cmd_t FCP_CMND;
/* SCSI INQUIRY Command Structure */
typedef struct emlxs_inquiryDataType {
typedef struct emlxs_read_capacity_data {
/* SCSI CDB command codes */
#define FCP_SCSI_FORMAT_UNIT 0x04
#define FCP_SCSI_INQUIRY 0x12
#define FCP_SCSI_MODE_SELECT 0x15
#define FCP_SCSI_MODE_SENSE 0x1A
#define FCP_SCSI_PAUSE_RESUME 0x4B
#define FCP_SCSI_PLAY_AUDIO 0x45
#define FCP_SCSI_PLAY_AUDIO_EXT 0xA5
#define FCP_SCSI_PLAY_AUDIO_MSF 0x47
#define FCP_SCSI_PLAY_AUDIO_TRK_INDX 0x48
#define FCP_SCSI_PREVENT_ALLOW_REMOVAL 0x1E
#define FCP_SCSI_READ_CMD 0x08
#define FCP_SCSI_READ_BUFFER 0x3C
#define FCP_SCSI_READ_CAPACITY 0x25
#define FCP_SCSI_READ_DEFECT_LIST 0x37
#define FCP_SCSI_READ_EXTENDED 0x28
#define FCP_SCSI_READ_HEADER 0x44
#define FCP_SCSI_READ_LONG 0xE8
#define FCP_SCSI_READ_SUB_CHANNEL 0x42
#define FCP_SCSI_READ_TOC 0x43
#define FCP_SCSI_REASSIGN_BLOCK 0x07
#define FCP_SCSI_RECEIVE_DIAGNOSTIC_RESULTS 0x1C
#define FCP_SCSI_RELEASE_UNIT 0x17
#define FCP_SCSI_REPORT_LUNS 0xa0
#define FCP_SCSI_REQUEST_SENSE 0x03
#define FCP_SCSI_RESERVE_UNIT 0x16
#define FCP_SCSI_REZERO_UNIT 0x01
#define FCP_SCSI_SEEK 0x0B
#define FCP_SCSI_SEEK_EXTENDED 0x2B
#define FCP_SCSI_SEND_DIAGNOSTIC 0x1D
#define FCP_SCSI_START_STOP_UNIT 0x1B
#define FCP_SCSI_TEST_UNIT_READY 0x00
#define FCP_SCSI_VERIFY 0x2F
#define FCP_SCSI_WRITE_CMD 0x0A
#define FCP_SCSI_WRITE_AND_VERIFY 0x2E
#define FCP_SCSI_WRITE_BUFFER 0x3B
#define FCP_SCSI_WRITE_EXTENDED 0x2A
#define FCP_SCSI_WRITE_LONG 0xEA
#define FCP_SCSI_RELEASE_LUNR 0xBB
#define FCP_SCSI_RELEASE_LUNV 0xBF
#define HPVA_SETPASSTHROUGHMODE 0x27
#define HPVA_EXECUTEPASSTHROUGH 0x29
#define HPVA_CREATELUN 0xE2
#define HPVA_SETLUNSECURITYLIST 0xED
#define HPVA_SETCLOCK 0xF9
#define HPVA_RECOVER 0xFA
#define HPVA_GENERICSERVICEOUT 0xFD
#define DMEP_EXPORT_IN 0x85
#define DMEP_EXPORT_OUT 0x89
#define MDACIOCTL_DIRECT_CMD 0x22
#define MDACIOCTL_STOREIMAGE 0x2C
#define MDACIOCTL_WRITESIGNATURE 0xA6
#define MDACIOCTL_SETREALTIMECLOCK 0xAC
#define MDACIOCTL_PASS_THRU_CDB 0xAD
#define MDACIOCTL_PASS_THRU_INITIATE 0xAE
#define MDACIOCTL_CREATENEWCONF 0xC0
#define MDACIOCTL_ADDNEWCONF 0xC4
#define MDACIOCTL_MORE 0xC6
#define MDACIOCTL_SETPHYSDEVPARAMETER 0xC8
#define MDACIOCTL_SETLOGDEVPARAMETER 0xCF
#define MDACIOCTL_SETCONTROLLERPARAMETER 0xD1
#define MDACIOCTL_WRITESANMAP 0xD4
#define MDACIOCTL_SETMACADDRESS 0xD5
/*
* End of FCP specific structures
*/
/* Fibre Channel Service Parameter definitions */
#define FF_FRAME_SIZE 2048
/* ==== Mailbox Commands ==== */
#define MBX_LOAD_SM 0x01
#define MBX_READ_NV 0x02
#define MBX_WRITE_NV 0x03
#define MBX_RUN_BIU_DIAG 0x04
#define MBX_INIT_LINK 0x05
#define MBX_DOWN_LINK 0x06
#define MBX_CONFIG_LINK 0x07
#define MBX_PART_SLIM 0x08
#define MBX_CONFIG_RING 0x09
#define MBX_RESET_RING 0x0A
#define MBX_READ_CONFIG 0x0B
#define MBX_READ_RCONFIG 0x0C
#define MBX_READ_SPARM 0x0D
#define MBX_READ_STATUS 0x0E
#define MBX_READ_RPI 0x0F
#define MBX_READ_XRI 0x10
#define MBX_READ_REV 0x11
#define MBX_READ_LNK_STAT 0x12
#define MBX_REG_LOGIN 0x13
#define MBX_UNREG_LOGIN 0x14
#define MBX_READ_LA 0x15
#define MBX_CLEAR_LA 0x16
#define MBX_DUMP_MEMORY 0x17
#define MBX_DUMP_CONTEXT 0x18
#define MBX_RUN_DIAGS 0x19
#define MBX_RESTART 0x1A
#define MBX_UPDATE_CFG 0x1B
#define MBX_DOWN_LOAD 0x1C
#define MBX_DEL_LD_ENTRY 0x1D
#define MBX_RUN_PROGRAM 0x1E
#define MBX_SET_MASK 0x20
#define MBX_SET_VARIABLE 0x21
#define MBX_UNREG_D_ID 0x23
#define MBX_KILL_BOARD 0x24
#define MBX_CONFIG_FARP 0x25
#define MBX_BEACON 0x2A
#define MBX_CONFIG_MSIX 0x30
#define MBX_HEARTBEAT 0x31
#define MBX_WRITE_VPARMS 0x32
#define MBX_ASYNC_EVENT 0x33
#define MBX_READ_EVENT_LOG_STATUS 0x37
#define MBX_READ_EVENT_LOG 0x38
#define MBX_WRITE_EVENT_LOG 0x39
#define MBX_NV_LOG 0x3A
#define MBX_LOAD_AREA 0x81
#define MBX_RUN_BIU_DIAG64 0x84
#define MBX_GET_DEBUG 0x86
#define MBX_CONFIG_PORT 0x88
#define MBX_READ_SPARM64 0x8D
#define MBX_READ_RPI64 0x8F
#define MBX_CONFIG_MSI 0x90
#define MBX_REG_LOGIN64 0x93
#define MBX_READ_LA64 0x95
#define MBX_FLASH_WR_ULA 0x98
#define MBX_SET_DEBUG 0x99
#define MBX_LOAD_EXP_ROM 0x9C
#define MBX_MAX_CMDS 0x9D
#define MBX_SLI2_CMD_MASK 0x80
/* ==== IOCB Commands ==== */
#define CMD_RCV_SEQUENCE_CX 0x01
#define CMD_XMIT_SEQUENCE_CR 0x02
#define CMD_XMIT_SEQUENCE_CX 0x03
#define CMD_XMIT_BCAST_CN 0x04
#define CMD_XMIT_BCAST_CX 0x05
#define CMD_QUE_RING_BUF_CN 0x06
#define CMD_QUE_XRI_BUF_CX 0x07
#define CMD_IOCB_CONTINUE_CN 0x08
#define CMD_RET_XRI_BUF_CX 0x09
#define CMD_ELS_REQUEST_CR 0x0A
#define CMD_ELS_REQUEST_CX 0x0B
#define CMD_RCV_ELS_REQ_CX 0x0D
#define CMD_ABORT_XRI_CN 0x0E
#define CMD_ABORT_XRI_CX 0x0F
#define CMD_CLOSE_XRI_CN 0x10
#define CMD_CLOSE_XRI_CX 0x11
#define CMD_CREATE_XRI_CR 0x12
#define CMD_CREATE_XRI_CX 0x13
#define CMD_GET_RPI_CN 0x14
#define CMD_XMIT_ELS_RSP_CX 0x15
#define CMD_GET_RPI_CR 0x16
#define CMD_XRI_ABORTED_CX 0x17
#define CMD_FCP_IWRITE_CR 0x18
#define CMD_FCP_IWRITE_CX 0x19
#define CMD_FCP_IREAD_CR 0x1A
#define CMD_FCP_IREAD_CX 0x1B
#define CMD_FCP_ICMND_CR 0x1C
#define CMD_FCP_ICMND_CX 0x1D
#define CMD_ADAPTER_MSG 0x20
#define CMD_ADAPTER_DUMP 0x22
/* LP3000 gasket IOCB Command Set */
#define CMD_BPL_IWRITE_CR 0x48
#define CMD_BPL_IWRITE_CX 0x49
#define CMD_BPL_IREAD_CR 0x4A
#define CMD_BPL_IREAD_CX 0x4B
#define CMD_BPL_ICMND_CR 0x4C
#define CMD_BPL_ICMND_CX 0x4D
#define CMD_ASYNC_STATUS 0x7C
/* SLI_2 IOCB Command Set */
#define CMD_RCV_SEQUENCE64_CX 0x81
#define CMD_XMIT_SEQUENCE64_CR 0x82
#define CMD_XMIT_SEQUENCE64_CX 0x83
#define CMD_XMIT_BCAST64_CN 0x84
#define CMD_XMIT_BCAST64_CX 0x85
#define CMD_QUE_RING_BUF64_CN 0x86
#define CMD_QUE_XRI_BUF64_CX 0x87
#define CMD_IOCB_CONTINUE64_CN 0x88
#define CMD_RET_XRI_BUF64_CX 0x89
#define CMD_ELS_REQUEST64_CR 0x8A
#define CMD_ELS_REQUEST64_CX 0x8B
#define CMD_RCV_ELS_REQ64_CX 0x8D
#define CMD_XMIT_ELS_RSP64_CX 0x95
#define CMD_FCP_IWRITE64_CR 0x98
#define CMD_FCP_IWRITE64_CX 0x99
#define CMD_FCP_IREAD64_CR 0x9A
#define CMD_FCP_IREAD64_CX 0x9B
#define CMD_FCP_ICMND64_CR 0x9C
#define CMD_FCP_ICMND64_CX 0x9D
#define CMD_RCV_SEQ_LIST64_CX 0xC1
#define CMD_GEN_REQUEST64_CR 0xC2
#define CMD_GEN_REQUEST64_CX 0xC3
#define CMD_QUE_RING_LIST64_CN 0xC6
/*
* Define Status
*/
#define MBX_SUCCESS 0
#define MBX_FAILURE 1
#define MBXERR_NUM_IOCBS 2
#define MBXERR_IOCBS_EXCEEDED 3
#define MBXERR_BAD_RING_NUMBER 4
#define MBXERR_MASK_ENTRIES_RANGE 5
#define MBXERR_MASKS_EXCEEDED 6
#define MBXERR_BAD_PROFILE 7
#define MBXERR_BAD_DEF_CLASS 8
#define MBXERR_BAD_MAX_RESPONDER 9
#define MBXERR_BAD_MAX_ORIGINATOR 0xA
#define MBXERR_RPI_REGISTERED 0xB
#define MBXERR_RPI_FULL 0xC
#define MBXERR_NO_RESOURCES 0xD
#define MBXERR_BAD_RCV_LENGTH 0xE
#define MBXERR_DMA_ERROR 0xF
#define MBXERR_NOT_SUPPORTED 0x10
#define MBXERR_UNSUPPORTED_FEATURE 0x11
#define MBXERR_UNKNOWN_COMMAND 0x12
/* Driver special codes */
#define MBX_OVERTEMP_ERROR 0xFA
#define MBX_HARDWARE_ERROR 0xFB
#define MBX_DRVR_ERROR 0xFC
#define MBX_BUSY 0xFD
#define MBX_TIMEOUT 0xFE
#define MBX_NOT_FINISHED 0xFF
/*
* flags for emlxs_mb_issue_cmd()
*/
typedef struct emlxs_rings {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef emlxs_rings_t RINGS;
typedef struct emlxs_ring_def {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef emlxs_ring_def_t RING_DEF;
/*
* The following F.C. frame stuctures are defined in Big Endian format.
*/
typedef struct emlxs_name_type {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define NAME_CCITT_TYPE 0xC
#define NAME_CCITT_GR_TYPE 0xE
typedef emlxs_name_type_t NAME_TYPE;
typedef struct emlxs_csp {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
struct {
} nPort;
} w2;
} emlxs_csp_t;
typedef emlxs_csp_t CSP;
typedef struct emlxs_class_parms {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef emlxs_class_parms_t CLASS_PARMS;
typedef struct emlxs_serv_parms { /* Structure is in Big Endian format */
typedef emlxs_serv_parms_t SERV_PARM;
typedef struct {
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
/* Emulex Organization Unique ID (00-00-C9) */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Emulex Organization Unique ID (00-00-C9) */
#endif
} w0;
} un0;
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} w1;
} un1;
/*
* Extended Link Service LS_COMMAND codes (Payload BYTE 0)
*/
#ifdef EMLXS_BIG_ENDIAN
#define ELS_CMD_SHIFT 24
#define ELS_CMD_MASK 0xff000000
#define ELS_RSP_MASK 0xff000000
#define ELS_CMD_LS_RJT 0x01000000
#define ELS_CMD_ACC 0x02000000
#define ELS_CMD_PLOGI 0x03000000
#define ELS_CMD_FLOGI 0x04000000
#define ELS_CMD_LOGO 0x05000000
#define ELS_CMD_ABTX 0x06000000
#define ELS_CMD_RCS 0x07000000
#define ELS_CMD_RES 0x08000000
#define ELS_CMD_RSS 0x09000000
#define ELS_CMD_RSI 0x0A000000
#define ELS_CMD_ESTS 0x0B000000
#define ELS_CMD_ESTC 0x0C000000
#define ELS_CMD_ADVC 0x0D000000
#define ELS_CMD_RTV 0x0E000000
#define ELS_CMD_RLS 0x0F000000
#define ELS_CMD_ECHO 0x10000000
#define ELS_CMD_TEST 0x11000000
#define ELS_CMD_RRQ 0x12000000
#define ELS_CMD_PRLI 0x20000000
#define ELS_CMD_PRLO 0x21000000
#define ELS_CMD_SCN 0x22000000
#define ELS_CMD_TPLS 0x23000000
#define ELS_CMD_GPRLO 0x24000000
#define ELS_CMD_GAID 0x30000000
#define ELS_CMD_FACT 0x31000000
#define ELS_CMD_FDACT 0x32000000
#define ELS_CMD_NACT 0x33000000
#define ELS_CMD_NDACT 0x34000000
#define ELS_CMD_QoSR 0x40000000
#define ELS_CMD_RVCS 0x41000000
#define ELS_CMD_PDISC 0x50000000
#define ELS_CMD_FDISC 0x51000000
#define ELS_CMD_ADISC 0x52000000
#define ELS_CMD_FARP 0x54000000
#define ELS_CMD_FARPR 0x55000000
#define ELS_CMD_FAN 0x60000000
#define ELS_CMD_RSCN 0x61000000
#define ELS_CMD_SCR 0x62000000
#define ELS_CMD_LINIT 0x70000000
#define ELS_CMD_RNID 0x78000000
#define ELS_CMD_AUTH 0x90000000
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#define ELS_CMD_SHIFT 0
#define ELS_CMD_MASK 0xff
#define ELS_RSP_MASK 0xff
#define ELS_CMD_LS_RJT 0x01
#define ELS_CMD_ACC 0x02
#define ELS_CMD_PLOGI 0x03
#define ELS_CMD_FLOGI 0x04
#define ELS_CMD_LOGO 0x05
#define ELS_CMD_ABTX 0x06
#define ELS_CMD_RCS 0x07
#define ELS_CMD_RES 0x08
#define ELS_CMD_RSS 0x09
#define ELS_CMD_RSI 0x0A
#define ELS_CMD_ESTS 0x0B
#define ELS_CMD_ESTC 0x0C
#define ELS_CMD_ADVC 0x0D
#define ELS_CMD_RTV 0x0E
#define ELS_CMD_RLS 0x0F
#define ELS_CMD_ECHO 0x10
#define ELS_CMD_TEST 0x11
#define ELS_CMD_RRQ 0x12
#define ELS_CMD_PRLI 0x20
#define ELS_CMD_PRLO 0x21
#define ELS_CMD_SCN 0x22
#define ELS_CMD_TPLS 0x23
#define ELS_CMD_GPRLO 0x24
#define ELS_CMD_GAID 0x30
#define ELS_CMD_FACT 0x31
#define ELS_CMD_FDACT 0x32
#define ELS_CMD_NACT 0x33
#define ELS_CMD_NDACT 0x34
#define ELS_CMD_QoSR 0x40
#define ELS_CMD_RVCS 0x41
#define ELS_CMD_PDISC 0x50
#define ELS_CMD_FDISC 0x51
#define ELS_CMD_ADISC 0x52
#define ELS_CMD_FARP 0x54
#define ELS_CMD_FARPR 0x55
#define ELS_CMD_FAN 0x60
#define ELS_CMD_RSCN 0x61
#define ELS_CMD_SCR 0x62
#define ELS_CMD_LINIT 0x70
#define ELS_CMD_RNID 0x78
#define ELS_CMD_AUTH 0x90
#endif
/*
* LS_RJT Payload Definition
*/
typedef struct _LS_RJT { /* Structure is in Big Endian format */
union {
struct {
/* LS_RJT reason codes */
#define LSRJT_INVALID_CMD 0x01
#define LSRJT_LOGICAL_ERR 0x03
#define LSRJT_LOGICAL_BSY 0x05
#define LSRJT_PROTOCOL_ERR 0x07
#define LSRJT_CMD_UNSUPPORTED 0x0B
/* LS_RJT reason explanation */
#define LSEXP_NOTHING_MORE 0x00
#define LSEXP_SPARM_OPTIONS 0x01
#define LSEXP_SPARM_ICTL 0x03
#define LSEXP_SPARM_RCTL 0x05
#define LSEXP_SPARM_RCV_SIZE 0x07
#define LSEXP_SPARM_CONCUR_SEQ 0x09
#define LSEXP_SPARM_CREDIT 0x0B
#define LSEXP_INVALID_PNAME 0x0D
#define LSEXP_INVALID_NNAME 0x0E
#define LSEXP_INVALID_CSP 0x0F
#define LSEXP_INVALID_ASSOC_HDR 0x11
#define LSEXP_ASSOC_HDR_REQ 0x13
#define LSEXP_INVALID_O_SID 0x15
#define LSEXP_INVALID_OX_RX 0x17
#define LSEXP_CMD_IN_PROGRESS 0x19
#define LSEXP_INVALID_NPORT_ID 0x1F
#define LSEXP_INVALID_SEQ_ID 0x21
#define LSEXP_INVALID_XCHG 0x23
#define LSEXP_INACTIVE_XCHG 0x25
#define LSEXP_RQ_REQUIRED 0x27
#define LSEXP_OUT_OF_RESOURCE 0x29
#define LSEXP_CANT_GIVE_DATA 0x2A
#define LSEXP_REQ_UNSUPPORTED 0x2C
} b;
} un;
} LS_RJT;
/*
*/
typedef struct _LOGO { /* Structure is in Big Endian format */
union {
struct {
} b;
} un;
} LOGO;
/*
* FCP Login (PRLI Request / ACC) Payload Definition
*/
#define PRLX_PAGE_LEN 0x10
#define TPRLO_PAGE_LEN 0x14
typedef struct _PRLI { /* Structure is in Big Endian format */
#define PRLI_FCP_TYPE 0x08
#ifdef EMLXS_BIG_ENDIAN
/* ACC = imagePairEstablished */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* ACC = imagePairEstablished */
#endif
#define PRLI_NO_RESOURCES 0x2
#define PRLI_INIT_INCOMPLETE 0x3
#define PRLI_NO_SUCH_PA 0x4
#define PRLI_PREDEF_CONFIG 0x5
#define PRLI_PARTIAL_SUCCESS 0x6
#define PRLI_INVALID_PAGE_CNT 0x7
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} PRLI;
/*
* FCP Logout (PRLO Request / ACC) Payload Definition
*/
typedef struct _PRLO { /* Structure is in Big Endian format */
#define PRLO_FCP_TYPE 0x08
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define PRLO_NO_SUCH_IMAGE 0x4
#define PRLO_INVALID_PAGE_CNT 0x7
} PRLO;
typedef struct _ADISC { /* Structure is in Big Endian format */
} ADISC;
typedef struct _FARP { /* Structure is in Big Endian format */
#define FARP_NO_ACTION 0 /* FARP info enclosed, no action */
} FARP;
typedef struct _FAN { /* Structure is in Big Endian format */
} FAN;
typedef struct _SCR { /* Structure is in Big Endian format */
#define SCR_FUNC_FABRIC 0x01
#define SCR_FUNC_NPORT 0x02
#define SCR_FUNC_FULL 0x03
#define SCR_CLEAR 0xff
} SCR;
typedef struct _RNID_TOP_DISC {
#define RNID_HBA 0x7
#define RNID_HOST 0xa
#define RNID_DRIVER 0xd
#define RNID_IPV4 0x1
#define RNID_IPV6 0x2
#define RNID_TD_SUPPORT 0x1
#define RNID_LP_VALID 0x2
typedef struct _RNID { /* Structure is in Big Endian format */
#define RNID_TOPOLOGY_DISC 0xdf
union {
} un;
} RNID;
typedef struct _RRQ { /* Structure is in Big Endian format */
} RRQ;
/* This is used for RSCN command */
typedef struct _D_ID { /* Structure is in Big Endian format */
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} b;
} un;
} D_ID;
/*
* Structure to define all ELS Payload types
*/
typedef struct _ELS_PKT { /* Structure is in Big Endian format */
union {
} un;
} ELS_PKT;
/*
* Begin Structure Definitions for Mailbox Commands
*/
typedef struct revcompat {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} REVCOMPAT;
typedef struct id_word {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
} un;
} PROG_ID;
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} RR_REG;
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ULP_BDE;
typedef struct ULP_BDE_64 { /* SLI-2 */
union ULP_BDE_TUS {
uint32_t w;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} f;
} tus;
} ULP_BDE64;
#define BDE64_SIZE_WORD 0
#define BPL64_SIZE_WORD 0x40
/* ULP */
typedef struct ULP_BPL_64 {
} ULP_BPL64;
typedef struct ULP_BDL { /* SLI-2 */
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ULP_BDL;
typedef struct {
void *data_handle;
void *dma_handle;
#define MAP_POOL_ALLOCATED 0x00000001
#define MAP_BUF_ALLOCATED 0x00000002
#define MAP_TABLE_ALLOCATED 0x00000004
} MATCHMAP;
/* Structure used for a HBQ entry */
typedef struct {
union UN_TAG {
uint32_t w;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ext;
} unt;
} HBQE_t;
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} HBQ_MASK;
#define EMLXS_MAX_HBQ_BUFFERS 4096
typedef struct {
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile2;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile3;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile5;
} profiles;
} HBQ_INIT_t;
/* Structure for MB Command LOAD_SM and DOWN_LOAD */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define DL_FROM_BDE 0 /* method */
#define DL_FROM_SLIM 1
#define PROGRAM_FLASH 0 /* erase_or_prog */
#define ERASE_FLASH 1
union {
} un;
} LOAD_SM_VAR;
/* Structure for MB Command READ_NVPARM (02) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_NV_VAR;
/* Structure for MB Command WRITE_NVPARMS (03) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} WRITE_NV_VAR;
/* Structure for MB Command RUN_BIU_DIAG (04) */
/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
typedef struct {
union {
struct {
} s1;
struct {
} s2;
} un;
} BIU_DIAG_VAR;
/* Structure for MB Command INIT_LINK (05) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* link_flags (=1) ENDEC loopback */
#define FLAGS_LOCAL_LB 0x01
#define LINK_SPEED_AUTO 0 /* Auto selection */
/* Structure for MB Command DOWN_LINK (06) */
typedef struct {
/* Structure for MB Command CONFIG_LINK (07) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CONFIG_LINK;
/* Structure for MB Command PART_SLIM (08) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command CONFIG_RING (09) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command RESET_RING (10) */
typedef struct {
/* Structure for MB Command READ_CONFIG (11) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Defines for topology (defined previously) */
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define LMT_1GB_CAPABLE 0x0004
#define LMT_2GB_CAPABLE 0x0008
#define LMT_4GB_CAPABLE 0x0040
#define LMT_8GB_CAPABLE 0x0080
#define LMT_10GB_CAPABLE 0x0100
/* E2E supported on adapters >= 8GB */
#ifdef SLI3_SUPPORT
#else
#endif /* SLI3_SUPPORT */
/* Structure for MB Command READ_RCONFIG (12) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command READ_SPARM (13) */
/* Structure for MB Command READ_SPARM64 (0x8D) */
typedef struct {
union {
} un;
/* Structure for MB Command READ_STATUS (14) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command READ_RPI (15) */
/* Structure for MB Command READ_RPI64 (0x8F) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
} un;
} READ_RPI_VAR;
/* Structure for MB Command READ_XRI (16) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_XRI_VAR;
/* Structure for MB Command READ_REV (17) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} b;
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_REV_VAR;
#define rxSeqRev postKernRev
/* Structure for MB Command READ_LINK_STAT (18) */
typedef struct {
} READ_LNK_VAR;
/* Structure for MB Command REG_LOGIN (19) */
/* Structure for MB Command REG_LOGIN64 (0x93) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
} un;
#ifdef SLI3_SUPPORT
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#endif /* SLI3_SUPPORT */
/* Word 30 contents for REG_LOGIN */
typedef union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} f;
} REG_WD30;
/* Structure for MB Command UNREG_LOGIN (20) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef SLI3_SUPPORT
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#endif /* SLI3_SUPPORT */
/* Structure for MB Command UNREG_D_ID (0x23) */
typedef struct {
#ifdef SLI3_SUPPORT
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#endif /* SLI3_SUPPORT */
/* Structure for MB Command READ_LA (21) */
/* Structure for MB Command READ_LA64 (0x95) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* lipType */
/* An L_PORT initing (F7, AL_PS) - lipType */
#define LT_PORT_INIT 0x00
/* Err @L_PORT rcv'er (F8, AL_PS) */
#define LT_PORT_ERR 0x01
/* Lip Reset of some other port */
#define LT_RESET_APORT 0x02
/* topology */
/* Topology is pt-pt pt-fabric */
#define TOPOLOGY_PT_PT 0x01
/* Topology is FC-AL (private) */
#define TOPOLOGY_LOOP 0x02
union {
/* This BDE points to a 128 byte buffer to */
/* store the LILP AL_PA position map into */
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_LA_VAR;
/* Structure for MB Command CLEAR_LA (22) */
typedef struct {
} CLEAR_LA_VAR;
/* Structure for MB Command DUMP */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} DUMP_VAR;
/*
* Dump type
*/
#define DMP_MEM_REG 0x1
#define DMP_NV_PARAMS 0x2
/*
* Dump region ID
*/
#define NODE_CFG_A_REGION_ID 0
#define NODE_CFG_B_REGION_ID 1
#define NODE_CFG_C_REGION_ID 2
#define NODE_CFG_D_REGION_ID 3
#define WAKE_UP_PARMS_REGION_ID 4
#define DEF_PCI_CFG_REGION_ID 5
#define PCI_CFG_1_REGION_ID 6
#define PCI_CFG_2_REGION_ID 7
#define RSVD1_REGION_ID 8
#define RSVD2_REGION_ID 9
#define RSVD3_REGION_ID 10
#define RSVD4_REGION_ID 11
#define RSVD5_REGION_ID 12
#define RSVD6_REGION_ID 13
#define RSVD7_REGION_ID 14
#define DIAG_TRACE_REGION_ID 15
#define WWN_REGION_ID 16
#define DMP_VPD_REGION 0xe
#define DMP_VPD_SIZE 1024
#define DMP_VPD_DUMP_WCOUNT 25
/* Structure for MB Command UPDATE_CFG */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#define INIT_REGION 1
#define UPDATE_DATA 2
#define CLEAN_UP_CFG 3
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#define INIT_REGION 1
#define UPDATE_DATA 2
#define CLEAN_UP_CFG 3
#endif
/* Structure for MB Command DEL_LD_ENTRY (29) */
typedef struct {
#ifdef EMLXS_LITTLE_ENDIAN
#else
#endif
#define FLASH_LOAD_LIST 1
#define RAM_LOAD_LIST 2
#define BOTH_LISTS 3
/* Structure for MB Command LOAD_AREA (81) */
typedef struct {
#ifdef EMLXS_LITTLE_ENDIAN
#else
#endif
union {
} un;
/* Structure for MB Command LOAD_EXP_ROM (9C) */
typedef struct {
#ifdef EMLXS_LITTLE_ENDIAN
#else
#endif
union {
} un;
/* Structure for MB Command CONFIG_HBQ (7C) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile2;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile3;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile5;
} profiles;
/* Structure for MB Command REG_VPI(0x96) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} REG_VPI_VAR;
/* Structure for MB Command UNREG_VPI (0x97) */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
} un;
/* Structure for MB Command CONFIG_PORT (0x88) */
#ifdef SLI3_SUPPORT
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#else /* !SLI3_SUPPORT */
typedef struct {
#endif /* SLI3_SUPPORT */
/* SLI-2 Port Control Block */
/* SLIM POINTER */
typedef struct _SLI2_RDSC {
} SLI2_RDSC;
typedef struct _PCB {
#ifdef EMLXS_BIG_ENDIAN
#define TYPE_NATIVE_SLI2 0x01;
#define FEATURE_INITIAL_SLI2 0x01;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#define FEATURE_INITIAL_SLI2 0x01;
#define TYPE_NATIVE_SLI2 0x01;
#endif
} PCB;
/* NEW_FEATURE */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* NEW_FEATURE */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* NEW_FEATURE */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Union of all Mailbox Command types */
typedef union {
} MAILVARIANTS;
#define MAILBOX_CMD_BSIZE 128
#define MAILBOX_CMD_WSIZE 32
/*
* SLI-2 specific structures
*/
typedef struct _SLI1_DESC {
} SLI1_DESC; /* 128 bytes */
typedef struct {
} HGP;
typedef struct {
} PGP;
#ifdef SLI3_SUPPORT
typedef struct _SLI2_DESC {
} SLI2_DESC; /* 128 bytes */
#else
typedef struct _SLI2_DESC {
} SLI2_DESC; /* 128 bytes */
#endif /* SLI3_SUPPORT */
typedef union {
} SLI_VAR;
typedef volatile struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} MAILBOX; /* 256 bytes */
/*
* End Structure Definitions for Mailbox Commands
*/
/*
* Begin Structure Definitions for IOCB Commands
*/
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* statAction FBSY reason codes */
/* statAction PBSY action codes */
/* statRsn LS_RJT reason codes defined in LS_RJT structure */
/* statRsn P_BSY reason codes */
/* statRsn BA_RJT reason codes */
/* LS_RJT reason explanation defined in LS_RJT structure */
/* BA_RJT reason explanation */
/* Local Reject errors */
#define IOERR_SUCCESS 0x00
#define IOERR_MISSING_CONTINUE 0x01
#define IOERR_SEQUENCE_TIMEOUT 0x02
#define IOERR_INTERNAL_ERROR 0x03
#define IOERR_INVALID_RPI 0x04
#define IOERR_NO_XRI 0x05
#define IOERR_ILLEGAL_COMMAND 0x06
#define IOERR_XCHG_DROPPED 0x07
#define IOERR_ILLEGAL_FIELD 0x08
/* RESERVED 0x09 */
/* RESERVED 0x0A */
#define IOERR_RCV_BUFFER_WAITING 0x0B
/* RESERVED 0x0C */
#define IOERR_TX_DMA_FAILED 0x0D
#define IOERR_RX_DMA_FAILED 0x0E
#define IOERR_ILLEGAL_FRAME 0x0F
/* RESERVED 0x10 */
#define IOERR_NO_RESOURCES 0x11
/* RESERVED 0x12 */
#define IOERR_ILLEGAL_LENGTH 0x13
#define IOERR_UNSUPPORTED_FEATURE 0x14
#define IOERR_ABORT_IN_PROGRESS 0x15
#define IOERR_ABORT_REQUESTED 0x16
#define IOERR_RCV_BUFFER_TIMEOUT 0x17
#define IOERR_LOOP_OPEN_FAILURE 0x18
#define IOERR_RING_RESET 0x19
#define IOERR_LINK_DOWN 0x1A
#define IOERR_CORRUPTED_DATA 0x1B
#define IOERR_CORRUPTED_RPI 0x1C
#define IOERR_OUT_OF_ORDER_DATA 0x1D
#define IOERR_OUT_OF_ORDER_ACK 0x1E
#define IOERR_DUP_FRAME 0x1F
#define IOERR_BAD_HOST_ADDRESS 0x21
#define IOERR_RCV_HDRBUF_WAITING 0x22
#define IOERR_MISSING_HDR_BUFFER 0x23
#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
#define IOERR_ABORTMULT_REQUESTED 0x25
/* RESERVED 0x26 */
/* RESERVED 0x27 */
#define IOERR_BUFFER_SHORTAGE 0x28
#define IOERR_XRIBUF_WAITING 0x29
/* RESERVED 0x2A */
#define IOERR_MISSING_HBQ_ENTRY 0x2B
#define IOERR_ABORT_EXT_REQ 0x2C
#define IOERR_CLOSE_EXT_REQ 0x2D
/* RESERVED 0x2E */
/* RESERVED 0x2F */
#define IOERR_XRIBUF_MISSING 0x30
#define IOERR_ASSI_RSP_SUPPRESSED 0x31
/* RESERVED 0x32 - 0x3F */
#define IOERR_ROFFSET_INVAL 0x40
#define IOERR_ROFFSET_MISSING 0x41
#define IOERR_INSUF_BUFFER 0x42
#define IOERR_MISSING_SI 0x43
#define IOERR_MISSING_ES 0x44
#define IOERR_INCOMP_XFER 0x45
/* RESERVED 0x46 - 0xFF */
/* Driver defined */
#define IOERR_ABORT_TIMEOUT 0xF0
} PARM_ERR;
typedef union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} hcsw;
} WORD5;
/* IOCB Command template for a generic response */
typedef struct {
} GENERIC_RSP;
/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
typedef struct {
/* IOCB Command template for ELS_REQUEST */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ELS_REQUEST;
/* IOCB Command template for RCV_ELS_REQ */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} RCV_ELS_REQ;
/* IOCB Command template for ABORT / CLOSE_XRI */
typedef struct {
#define ABORT_TYPE_ABTX 0x00000000
#define ABORT_TYPE_ABTS 0x00000001
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} AC_XRI;
/* IOCB Command template for GET_RPI */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} GET_RPI;
/* IOCB Command template for all FCP Initiator commands */
typedef struct {
} FCPI_FIELDS;
/* IOCB Command template for all FCP Target commands */
typedef struct {
} FCPT_FIELDS;
/* SLI-2 IOCB structure definitions */
/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
typedef struct {
/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
typedef struct {
/* IOCB Command template for ELS_REQUEST64 */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* IOCB Command template for ASYNC_STATUS */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ASYNC_STATUS;
/* IOCB Command template for QUE_RING_LIST64 */
typedef struct {
/* IOCB Command template for GEN_REQUEST64 */
typedef struct {
/* IOCB Command template for RCV_ELS_REQ64 */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* IOCB Command template for all 64 bit FCP Initiator commands */
typedef struct {
/* IOCB Command template for all 64 bit FCP Target commands */
typedef struct {
/* IOCB Command template for all 64 bit FCP Target commands */
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif /* EMLXS_BIG_ENDIAN */
#ifdef EMLXS_LITTLE_ENDIAN
#endif /* EMLXS_LITTLE_ENDIAN */
} AUTO_TRSP;
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/*
* IOCB Command Extension template for CMD_RCV_ELS64_CX (0xB7)
* or CMD_RCV_SEQ64_CX (0xB5)
*/
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef volatile struct emlxs_iocb { /* IOCB structure */
union {
/* SLI-2 structures */
} un;
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} t1;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} t2;
} un1;
#define IOCB_DELAYXMIT_MSK 0x3000
union {
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} t1;
struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} t2;
} un2;
/* 32 bytes at this point */
#ifdef SLI3_SUPPORT
union {
} unsli3;
/* 128 bytes at this point */
#endif /* SLI3_SUPPORT */
#define PARM_UNUSED 0 /* PU field (Word 4) not used */
#define CLASS1 0 /* Class 1 */
#define IOSTAT_FCP_RSP_ERROR 0x1
#define IOSTAT_REMOTE_STOP 0x2
#define IOSTAT_LOCAL_REJECT 0x3
#define IOSTAT_NPORT_RJT 0x4
#define IOSTAT_FABRIC_RJT 0x5
#define IOSTAT_NPORT_BSY 0x6
#define IOSTAT_FABRIC_BSY 0x7
#define IOSTAT_INTERMED_RSP 0x8
#define IOSTAT_LS_RJT 0x9
#define IOSTAT_RESERVED_A 0xA
#define IOSTAT_CMD_REJECT 0xB
#define IOSTAT_FCP_TGT_LENCHK 0xC
#define IOSTAT_NEED_BUF_ENTRY 0xD
#define IOSTAT_RESERVED_E 0xE
#define IOSTAT_ILLEGAL_FRAME_RCVD 0xF
/* Special error codes */
} emlxs_iocb_t;
typedef emlxs_iocb_t IOCB;
typedef struct emlxs_iocbq {
struct emlxs_iocbq *next;
void *port; /* Board info pointer */
void *ring; /* Ring pointer */
void *node; /* Node pointer */
void *sbp; /* Pkt pointer */
#define IOCB_POOL_ALLOCATED 0x00000001
#define IOCB_PRIORITY 0x00000002
#define IOCB_SPECIAL 0x00000004
typedef emlxs_iocbq_t IOCBQ;
typedef struct emlxs_mbq {
/* Defferred handling pointers */
#define MBQ_POOL_ALLOCATED 0x00000001
#define MBQ_PASSTHRU 0x00000002
#define MBQ_INIT_MASK 0x0000ffff
#ifdef MBOX_EXT_SUPPORT
#endif /* MBOX_EXT_SUPPORT */
} emlxs_mbq_t;
typedef emlxs_mbq_t MAILBOXQ;
/* We currently do not support IOCBs in SLI1 mode */
typedef struct {
#ifdef MBOX_EXT_SUPPORT
#endif /* MBOX_EXT_SUPPORT */
} SLIM1;
typedef struct {
#ifdef MBOX_EXT_SUPPORT
#endif /* MBOX_EXT_SUPPORT */
} SLIM2;
/*
* This file defines the Header File for the FDMI HBA Management Service
*/
/*
* FDMI HBA MAnagement Operations Command Codes
*/
/*
* Management Service Subtypes
*/
#define SLI_CT_FDMI_Subtypes 0x10
/*
* HBA Management Service Reject Code
*/
/*
* HBA Management Service Reject Reason Code
* Please refer to the Reason Codes above
*/
/*
* HBA Attribute Types
*/
#define NODE_NAME 0x1
#define MANUFACTURER 0x2
#define SERIAL_NUMBER 0x3
#define MODEL 0x4
#define MODEL_DESCRIPTION 0x5
#define HARDWARE_VERSION 0x6
#define DRIVER_VERSION 0x7
#define OPTION_ROM_VERSION 0x8
#define FIRMWARE_VERSION 0x9
#define VENDOR_SPECIFIC 0xa
#define DRV_NAME 0xb
#define OS_NAME_VERSION 0xc
#define MAX_CT_PAYLOAD_LEN 0xd
/*
* Port Attrubute Types
*/
#define SUPPORTED_FC4_TYPES 0x1
#define SUPPORTED_SPEED 0x2
#define PORT_SPEED 0x3
#define MAX_FRAME_SIZE 0x4
#define OS_DEVICE_NAME 0x5
union AttributesDef {
/* Structure is in Big Endian format */
struct {
} bits;
};
/*
* HBA Attribute Entry (8 - 260 bytes)
*/
typedef struct {
union AttributesDef ad;
union {
} un;
/*
* HBA Attribute Block
*/
typedef struct {
/*
* Port Entry
*/
typedef struct {
} PORT_ENTRY, *PPORT_ENTRY;
/*
* HBA Identifier
*/
typedef struct {
/*
* Registered Port List Format
*/
typedef struct {
/*
* Register HBA(RHBA)
*/
typedef struct {
/* ATTRIBUTE_BLOCK ab; */
/*
* Register HBA Attributes (RHAT)
*/
typedef struct {
/*
* Register Port Attributes (RPA)
*/
typedef struct {
/*
* Get Registered HBA List (GRHL) Accept Payload Format
*/
typedef struct {
/*
* Get Registered Port List (GRPL) Accept Payload Format
*/
typedef struct {
/*
* Get Port Attributes (GPAT) Accept Payload Format
*/
typedef struct {
/*
* Use for Firmware DownLoad
*/
/* ------------------------ download.h ------------------------------ */
#define SLI_FW_TYPE_SHIFT(x) ((x << 20))
#define SLI_FW_ADAPTER_TYPE_MASK 0x00f00000
#define SLI_FW_TYPE_6000 SLI_FW_TYPE_SHIFT(0)
enum emlxs_prog_type {
TEST_PROGRAM, /* 0 */
UTIL_PROGRAM, /* 1 */
FUNC_FIRMWARE, /* 2 */
BOOT_BIOS, /* 3 */
CONFIG_DATA, /* 4 */
SEQUENCER_CODE, /* 5 */
SLI1_OVERLAY, /* 6 */
SLI2_OVERLAY, /* 7 */
GASKET, /* 8 */
HARDWARE_IMAGE, /* 9 */
SBUS_FCODE, /* A */
SLI3_OVERLAY, /* B */
SLI4_OVERLAY, /* E */
KERNEL_CODE, /* F */
typedef struct emlxs_fw_file {
char label[16];
typedef struct emlxs_fw_image {
#define NOP_IMAGE_TYPE 0xe1a00000
#define FLASH_BASE_ADR 0x01400000
#ifdef MBOX_EXT_SUPPORT
#else
#define DL_SLIM_SEG_BYTE_COUNT 128
#endif /* MBOX_EXT_SUPPORT */
#define SLI_CKSUM_LENGTH 4
#define SLI_CKSUM_SEED 0x55555555
#define SLI_CKSUM_ERR 0x1982abcd
#define AIF_NOOP 0xe1a00000
#define AIF_BLAL 0xeb000000
#define OS_EXIT 0xef000011
#define OS_GETENV 0xef000010
#define AIF_IMAGEBASE 0x00008000
#define AIF_BLZINIT 0xeb00000c
#define DEBUG_TASK 0xef041d41
#define AIF_DBG_SRC 2
#define AIF_DBG_LL 1
#define AIF_DATABASAT 0x100
#define JEDEC_ID_ADDRESS 0x0080001c
#define MAX_RBUS_SRAM_SIZE_ADR 0x788
#define MAX_IBUS_SRAM_SIZE_ADR 0x78c
#define FULL_RBUS_SRAM_CFG 0x7fffc
#define FULL_IBUS_SRAM_CFG 0x187fffc
#define REDUCED_RBUS_SRAM_CFG 0x5fffc
#define REDUCED_IBUS_SRAM_CFG 0x183fffc
#define FULL_SRAM_CFG_PROG_ID 1
#define REDUCED_SRAM_CFG_PROG_ID 2
#define OTHER_SRAM_CFG_PROG_ID 3
#define NO_FLASH_MEM_AVAIL 0xf1
#define PROG_TYPE_MASK 0xff000000
#define PROG_TYPE_SHIFT 24
#define FLASH_LOAD_LIST_ADR 0x79c
#define RAM_LOAD_ENTRY_SIZE 9
#define FLASH_LOAD_ENTRY_SIZE 6
#define RAM_LOAD_ENTRY_TYPE 0
#define FLASH_LOAD_ENTRY_TYPE 1
#define CFG_DATA_NO_REGION -3
#define SLI_IMAGE_START 0x20080
#define SLI_VERSION_LOC 0x270
/* def for new 2MB Flash (Pegasus ...) */
#define MBX_LOAD_AREA 0x81
#define MBX_LOAD_EXP_ROM 0x9C
#define FILE_TYPE_AWC 0xE1A01001
#define FILE_TYPE_DWC 0xE1A02002
#define FILE_TYPE_BWC 0xE1A03003
#define AREA_ID_MASK 0xFFFFFF0F
#define AREA_ID_AWC 0x00000001
#define AREA_ID_DWC 0x00000002
#define AREA_ID_BWC 0x00000003
#define CMD_START_ERASE 1
#define CMD_CONTINUE_ERASE 2
#define CMD_DOWNLOAD 3
#define CMD_END_DOWNLOAD 4
#define RSP_ERASE_STARTED 1
#define RSP_ERASE_COMPLETE 2
#define RSP_DOWNLOAD_MORE 3
#define RSP_DOWNLOAD_DONE 4
#define EROM_CMD_FIND_IMAGE 8
#define EROM_CMD_CONTINUE_ERASE 9
#define EROM_CMD_COPY 10
#define EROM_RSP_ERASE_STARTED 8
#define EROM_RSP_ERASE_COMPLETE 9
#define EROM_RSP_COPY_MORE 10
#define EROM_RSP_COPY_DONE 11
#define ALLext 1
#define DWCext 2
#define BWCext 3
#define NO_ALL 0
#define ALL_WITHOUT_BWC 1
#define ALL_WITH_BWC 2
#define KERNEL_START_ADDRESS 0x000000
#define DOWNLOAD_START_ADDRESS 0x040000
#define EXP_ROM_START_ADDRESS 0x180000
#define SCRATCH_START_ADDRESS 0x1C0000
#define CONFIG_START_ADDRESS 0x1E0000
typedef struct SliAifHdr {
typedef struct ImageHdr {
} IMAGE_HDR, *PIMAGE_HDR;
typedef struct {
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union {
} u0;
union {
} u1;
#define PROG_DESCR_STR_LEN 24
#define MAX_LOAD_ENTRY 10
typedef struct {
union {
} un;
} LOAD_ENTRY;
typedef struct {
} LOAD_LIST;
#define SLI_HW_REVISION_CHECK(x, y) ((x & 0xf0) == y)
#define SLI_FCODE_REVISION_CHECK(x, y) (x == y)
/* Define the adapters */
#include <emlxs_adapters.h>
#ifdef __cplusplus
}
#endif
#endif /* _EMLXS_HW_H */