/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2004-2011 Emulex. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _EMLXS_HW_H
#define _EMLXS_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/* (includes physical port) */
/* operation */
/*
* Total: 184 Cmd's + 184 Rsp's = 368
* Command and response entry counts are not required to be equal
*/
/* SLI1 Definitions */
/* SLI2 Definitions */
(SLI2_IOCB_RSP_SIZE * \
/* SLI3 Definitions */
(SLI3_IOCB_RSP_SIZE * \
/* These two are defined to indicate FCP cmd or non FCP cmd */
#define FC_FCP_CMD 0
#define FC_FCT_CMD 0
/* iocb */
/* area */
/*
* Miscellaneous stuff....
*/
/* HBA Mgmt */
#define END_OF_CHAIN 0
/* defines for type field in fc header */
/* defines for rctl field in fc header */
/*
* Common Transport structures and definitions
*
*/
#define EMLXS_COMMAND 0
typedef union CtRevisionId
{
/* Structure is in Big Endian format */
struct
{
} bits;
typedef union CtCommandResponse
{
/* Structure is in Big Endian format */
struct
{
} bits;
typedef struct SliCtRequest
{
/* Structure is in Big Endian format */
union
{
struct gid
{
} gid;
struct rft
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} rft;
struct rsnn
{
} rsnn;
struct rspn
{
} rspn;
} un;
/*
* FsType Definitions
*/
/*
* Directory Service Subtypes
*/
/*
* Response Codes
*/
/*
* Reason Codes
*/
/*
* Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
*/
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/*
* Management Server Interface Command Codes
*/
/*
* Name Server Command Codes
*/
/*
* Port Types
*/
/* ===================================================================== */
/*
* Start FireFly Register definitions
*/
/* PCI register offsets */
/* General PCI Register Definitions */
/* Refer To The PCI Specification For Detailed Explanations */
/* PCI capatability registers are defined in pci.h */
#define PCI_CAP_ID_SHIFT 0
/* PCI extended capatability registers are defined in pcie.h */
/* Vendor Specific (VS) register */
/* PCI access methods */
/* max number of pci buses */
/* number of PCI config bytes to access */
/* PCI related constants */
/* PCI addresses */
/* for FF11.1N6 firmware. */
/* Use 0x80 for pre-FF11.1N6 */
/* &N7, etc */
/* ==== Register Bit Definitions ==== */
/* Used by SBUS adapter */
/* SBUS Control Register */
/* lowset priority */
/* SBUS Status Register */
/* SBUS Update Register */
/* Host Attention Register */
#ifdef MSI_SUPPORT
/* Host attention interrupt map */
#define EMLXS_MSI_MAP1 {0, 0, 0, 0, 0, 0, 0, 0}
/* MSI 0 interrupt mask */
#define EMLXS_MSI0_MASK8 0
#define EMLXS_MSI_MODE1 0
#endif /* MSI_SUPPORT */
/* Chip Attention Register */
/* Host Status Register */
/* Host Control Register */
/* BIU Configuration Register */
/*
* End FireFly Register definitions
*/
/*
* Start SLI 4 section.
*/
/* PCI Config Register offsets */
/* BAR1 and BAR2 register offsets */
/* BAR1 offsets for principal registers */
/* MPU EP Semaphore register (ARM POST) */
/* SLI Status register */
/* SLI Control register */
/* SLI PHYDEV Control register */
/* POST Stages of interest */
/* BAR2 offsets for principal doorbell registers */
/* Doorbell definitions */
/* Defines for MQ doorbell */
/* Defines for CQ doorbell */
/* Defines for EQ doorbell */
/* bootstrap mailbox doorbell defines */
/* Sizeof bootstrap mailbox */
/* ===================================================================== */
/*
* Start of FCP specific structures
*/
typedef struct emlxs_fcp_rsp
{
/* in fcpStatus2. */
/* Received in Big Endian format */
/* Received in Big Endian format */
/* in fcpRspInfo */
/* Received in Big Endian format */
/*
* Define maximum size of SCSI Sense buffer.
* Seagate never issues more than 18 bytes of Sense data
*/
typedef struct emlxs_fcp_cmd
{
/*
* # of bits to shift lun id to end up in right payload word,
* little endian = 8, big = 16.
*/
#ifdef EMLXS_LITTLE_ENDIAN
#define FC_ADDR_MODE_SHIFT 0
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
/* codes */
/* SCSI INQUIRY Command Structure */
typedef struct emlxs_inquiryDataType
{
typedef struct emlxs_read_capacity_data
{
/* SCSI CDB command codes */
/*
* End of FCP specific structures
*/
/* Fibre Channel Service Parameter definitions */
typedef struct emlxs_rings
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct emlxs_ring_def
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/*
* The following F.C. frame stuctures are defined in Big Endian format.
*/
typedef struct emlxs_name_type
{
#ifdef EMLXS_BIG_ENDIAN
/* of IEEE ext */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* of IEEE ext */
#endif
/* IEEE extended Lsb */
/*
* Word 1 Bit 31 in common service parameter is overloaded.
*/
typedef struct emlxs_csp
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
struct
{
} nPort;
/* Endian format */
} w2;
/* Endian format */
} emlxs_csp_t;
typedef struct emlxs_class_parms
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct emlxs_serv_parms
{ /* Structure is in Big Endian format */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
/* Unique ID (0000C9) */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Unique ID (0000C9) */
#endif
} w0;
} un0;
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} w1;
} un1;
/*
* Extended Link Service LS_COMMAND codes (Payload BYTE 0)
*/
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#define ELS_CMD_SHIFT 0
#endif
/*
* LS_RJT Payload Definition
*/
typedef struct _LS_RJT
{ /* Structure is in Big Endian format */
union
{
struct
{
/* bit 24:31 */
/* bit 16:23 */
/* LS_RJT reason codes */
/* bit 8:15 */
/* LS_RJT reason explanation */
} b;
} un;
} LS_RJT;
/*
*/
typedef struct _LOGO
{ /* Structure is in Big Endian format */
union
{
struct
{
} b;
} un;
} LOGO;
/*
* FCP Login (PRLI Request / ACC) Payload Definition
*/
typedef struct _PRLI
{ /* Structure is in Big Endian format */
#ifdef EMLXS_BIG_ENDIAN
/* ACC = imagePairEstablished */
/* ACC ONLY */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* ACC ONLY */
/* ACC = imagePairEstablished */
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} PRLI;
/*
* FCP Logout (PRLO Request / ACC) Payload Definition
*/
typedef struct _PRLO
{ /* Structure is in Big Endian format */
#ifdef EMLXS_BIG_ENDIAN
/* ACC ONLY */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* ACC ONLY */
#endif
} PRLO;
typedef struct _ADISC
{ /* Structure is in Big Endian format */
} ADISC;
typedef struct _FARP
{ /* Structure is in Big Endian format */
} FARP;
typedef struct _FAN
{ /* Structure is in Big Endian format */
} FAN;
typedef struct _SCR
{ /* Structure is in Big Endian format */
} SCR;
typedef struct _RNID_TOP_DISC
{
typedef struct _RNID
{ /* Structure is in Big Endian format */
union
{
} un;
} RNID;
typedef struct _RRQ
{ /* Structure is in Big Endian format */
} RRQ;
/* This is used for RSCN command */
typedef struct _D_ID
{ /* Structure is in Big Endian format */
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} b;
} un;
} D_ID;
/*
* Structure to define all ELS Payload types
*/
typedef struct _ELS_PKT
{ /* Structure is in Big Endian format */
union
{
/* PDISC, ACC */
/* ACC */
/* 128 bytes */
} un;
} ELS_PKT;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ULP_BDE;
typedef struct ULP_BDE_64
{ /* SLI-2 */
union ULP_BDE_TUS
{
uint32_t w;
struct
{
#ifdef EMLXS_BIG_ENDIAN
/* SUPPORTED VALUE !! */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* SUPPORTED VALUE !! */
#endif
/* 0=xmit buffer */
/* 0=64 bit addr */
} f;
} tus;
} ULP_BDE64;
#define BDE64_SIZE_WORD 0
/* ULP */
typedef struct ULP_BPL_64
{
} ULP_BPL64;
typedef struct ULP_BDL
{ /* SLI-2 */
#ifdef EMLXS_BIG_ENDIAN
/* memory (bytes) */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* memory (bytes) */
#endif
} ULP_BDL;
typedef struct ULP_SGE_64
{ /* SLI-4 */
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ULP_SGE64;
typedef struct _BE_PHYS_ADDR
{
} BE_PHYS_ADDR;
typedef struct
{
void *fc_mptr;
void *data_handle;
void *dma_handle;
#ifdef SFCT_SUPPORT
void *fct_private;
#endif /* SFCT_SUPPORT */
} MATCHMAP;
/*
* This file defines the Header File for the FDMI HBA Management Service
*/
/*
* FDMI HBA MAnagement Operations Command Codes
*/
/*
* Management Service Subtypes
*/
/*
* HBA Management Service Reject Code
*/
/*
* HBA Management Service Reject Reason Code
* Please refer to the Reason Codes above
*/
/*
* HBA Attribute Types
*/
/*
* Port Attrubute Types
*/
union AttributesDef
{
/* Structure is in Big Endian format */
struct
{
} bits;
};
/*
* HBA Attribute Entry (8 - 260 bytes)
*/
typedef struct
{
union
{
} un;
/*
* HBA Attribute Block
*/
typedef struct
{
/*
* Port Entry
*/
typedef struct
{
/*
* HBA Identifier
*/
typedef struct
{
/*
* Registered Port List Format
*/
typedef struct
{
/*
* Register HBA(RHBA)
*/
typedef struct
{
/*
* Register HBA Attributes (RHAT)
*/
typedef struct
{
/*
* Register Port Attributes (RPA)
*/
typedef struct
{
/*
* Get Registered HBA List (GRHL) Accept Payload Format
*/
typedef struct
{
/*
* Get Registered Port List (GRPL) Accept Payload Format
*/
typedef struct
{
/*
* Get Port Attributes (GPAT) Accept Payload Format
*/
typedef struct
{
/*
* Use for Firmware DownLoad
*/
/* download.h */
enum emlxs_prog_type
{
typedef struct emlxs_fw_file
{
typedef struct emlxs_fw_image
{
#ifdef MBOX_EXT_SUPPORT
#else
#endif /* MBOX_EXT_SUPPORT */
#define RAM_LOAD_ENTRY_TYPE 0
#define SLI_FCODE_REVISION_CHECK(x, y) (x == y)
/* ************ OBJ firmware ************** */
/* ************ BladeEngine ************** */
/* ************** BE3 **************** */
typedef struct emlxs_be3_image_header
{
typedef struct emlxs_be3_ufi_header
{
typedef struct emlxs_be3_ufi_controller
{
typedef struct emlxs_be3_flash_header
{
typedef struct emlxs_be3_flash_entry
{
typedef struct emlxs_be3_flash_dir
{
typedef struct emlxs_be3_ncsi_header {
/* ************** BE2 **************** */
typedef struct emlxs_be2_ufi_controller
{
typedef struct emlxs_be2_ufi_header
{
{
typedef struct emlxs_be2_flash_entry
{
typedef struct emlxs_be2_flash_dir
{
/* FLASH ENTRY TYPES */
/* Flash types in download order */
typedef enum emlxs_be_flashtypes
{
/* Driver level constructs */
typedef struct emlxs_be_fw_file
{
typedef struct emlxs_be_fw_image
{
typedef struct emlxs_obj_header
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef __cplusplus
}
#endif
#endif /* _EMLXS_HW_H */