/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_DMA_I8237A_H
#define _SYS_DMA_I8237A_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
/* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
/* All Rights Reserved */
/*
* Defines for PC AT DMA controllers.
*/
/*
*/
/*
* The Intel DMA controllers are augmented with 8-bit page registers
* for each channel, allowing access to a 16MB address space.
*/
/*
* The EISA has an 8-bit high-page register for each channel
* for access to a 32-bit address space.
*/
/* high page reg */
/* high page reg */
/* high page reg */
/* high page reg */
/* high page reg */
/* high page reg */
/* high page reg */
/* high page reg */
/*
* The EISA has an 8-bit high-count register for each channel
* for xfer sizes up to 16MB.
*/
/*
* I/O port addresses for controller 1
*/
/*
* I/O port addresses for controller 2
*/
/*
* Write-only Command register definitions.
*/
/*
* Initialization value for DMA controller.
*/
/*
* Write-only Mode register. There is actually a 6-bit Mode register
* associated with each channel. These are written one at a time, with
* the channel number indicated by the low-order 2 bits.
*/
/* These indicate channel 0-3 */
/* Note: Above settings for bits 2-3 are */
/* "don't care" if bits 6-7 indicate */
/* cascade mode */
/* Each DREQ causes transfers at full speed */
/* until DREQ goes inactive (after which it */
/* can be resumed) or either terminal-count */
/* happens or EOP is asserted */
/* Each DREQ causes transfers at full speed */
/* until terminal count or EOP */
/* should be set for DMA 2 channel 0 ONLY */
/*
* DMA Channels. d_chan field of dmareq.
*/
/* 8 bit channels */
/* 16 bit channels */
/*
* DMA Masks.
*/
/* dma_alloc modes */
/*
* Channel Address Array - makes life much easier
*/
struct d37A_chan_reg_addr {
};
/*
* macro to initialize array of d37A_chan_reg_addr structures
*/
#define D37A_BASE_REGS_VALUES \
extern int d37A_init(dev_info_t *);
extern void d37A_dma_disable(int);
extern void d37A_dma_enable(int);
extern void d37A_dma_swstart(int);
extern void d37A_dma_stop(int);
extern void d37A_get_chan_stat(int, ulong_t *, int *);
extern int d37A_dma_valid(int);
extern void d37A_dma_release(int);
/* The following 3 routines are intel specific : man page ddi_dmae_req(9S) */
#endif
#ifdef __cplusplus
}
#endif
#endif /* _SYS_DMA_I8237A_H */