agpdefs.h revision 5dbcb2a2ded752a6731e3db12a239d1380080da3
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Use is subject to license terms.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#pragma ident "%Z%%M% %I% %E% SMI"
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinextern "C" {
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * This AGP memory type is required by some hadrware like i810 video
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * card, which need physical contiguous pages to setup hardware cursor.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Usually, several tens of kilo bytes are needed in this case.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * We use DDI DMA interfaces to allocate such memory in agpgart driver,
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * and it can not be exported to user applications directly by calling mmap
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * on agpgart driver. The typical usage scenario is as the following:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * on agpgart driver. Secondly, Xserver use the physical address to mmap
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * the memory to Xserver space area by xsvc driver.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define AGP_PHYSICAL 2 /* Only used for i810, HW curosr */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* AGP space units */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define AGP_ALIGNED(offset) (((offset) & AGP_PAGE_OFFSET) == 0)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* stand pci register offset */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* macros for device types */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define DEVICE_IS_I810 11 /* intel i810 series video card */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define DEVICE_IS_I830 12 /* intel i830, i845, i855 series */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* AGP bridge device id */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define INTEL_BR_815 0x11308086 /* include 815G/EG/P/EP */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define INTEL_BR_855GM 0x35808086 /* include 852GM/PM */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* AGP common register offset in pci configuration space */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/* AGP target register and mask defines */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define AGP_32_APERBASE_MASK 0xffc00000 /* 4M aligned */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#define AGP_64_APERBASE_MASK 0xffffc00000LL /* 4M aligned */
#ifdef __cplusplus