/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2009, Intel Corporation.
* All Rights Reserved.
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_AGPDEFS_H
#define _SYS_AGPDEFS_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* This AGP memory type is required by some hardware like i810 video
* card, which need physical contiguous pages to setup hardware cursor.
* Usually, several tens of kilo bytes are needed in this case.
* We use DDI DMA interfaces to allocate such memory in agpgart driver,
* and it can not be exported to user applications directly by calling mmap
* on agpgart driver. The typical usage scenario is as the following:
* Firstly, Xserver get the memory physical address by calling AGPIOC_ALLOCATE
* on agpgart driver. Secondly, Xserver use the physical address to mmap
* the memory to Xserver space area by xsvc driver.
*
*/
#ifdef _KERNEL
/* AGP space units */
/* stand pci register offset */
/* macros for device types */
/* AGP bridge device id */
/* AGP common register offset in pci configuration space */
/* AGP target register and mask defines */
/* AGP gart table definition */
/* AGP term definitions */
/* Intel integrated video card, chipset id */
/* Intel 915 and 945 series */
(device == INTEL_IGD_915GM) || \
(device == INTEL_IGD_945) || \
(device == INTEL_IGD_945GM) || \
(device == INTEL_IGD_945GME))
/* Intel 965 series */
(device == INTEL_IGD_965G1) || \
(device == INTEL_IGD_965Q) || \
(device == INTEL_IGD_965G2) || \
(device == INTEL_IGD_965GM) || \
(device == INTEL_IGD_965GME) || \
(device == INTEL_IGD_GM45) || \
/* Intel G33 series */
(device == INTEL_IGD_G33) || \
(device == INTEL_IGD_Q33))
/* IGDNG */
(device == INTEL_IGD_IGDNG_M))
/* Intel G4X series */
(device == INTEL_IGD_Q45) || \
(device == INTEL_IGD_G45) || \
(device == INTEL_IGD_G41) || \
(device == INTEL_IGD_B43))
/* register offsets in PCI config space */
/* (Mirror) GMCH Graphics Control Register (GGC, MGGC) */
/* Intel integrated video card graphics mode mask */
/* GTT Graphics Memory Size (9:8) in GMCH Graphics Control Register */
/* No VT mode, 1MB allocated for GTT */
/* VT mode, 2MB allocated for GTT */
/* Intel integrated video card GTT definition */
/* Intel i810 register offset */
/*
* GART and GTT entry format table
*
* AMD64 GART entry
* from bios and kernel develop guide for amd64
* -----------------------------
* Bits Description |
* 0 valid |
* 1 coherent |
* 3:2 reserved |
* 11:4 physaddr[39:32] |
* 31:12 physaddr[31:12] |
* -----------------------------
* Intel GTT entry
* Intel video programming manual
* -----------------------------
* Bits descrition |
* 0 valid |
* 2:1 memory type |
* 29:12 PhysAddr[29:12] |
* 31:30 reserved |
* -----------------------------
* AGP entry
* from AGP protocol 3.0
* -----------------------------
* Bits descrition |
* 0 valid |
* 1 coherent |
* 3:2 reserved |
* 11:4 PhysAddr[39:32] |
* 31:12 PhysAddr[31:12] |
* 63:32 PhysAddr[71:40] |
* -----------------------------
*/
/*
* gart and gtt table base register format
*
* AMD64 register format
* from bios and kernel develop guide for AMD64
* ---------------------------------------------
* Bits Description |
* 3:0 reserved |
* 31:4 physical addr 39:12 |
* ----------------------------------------------
* INTEL AGPGART table base register format
* from AGP protocol 3.0 p142, only support 32 bits
* ---------------------------------------------
* Bits Description |
* 11:0 reserved |
* 31:12 physical addr 31:12 |
* 63:32 physical addr 63:32 |
* ---------------------------------------------
* INTEL i810 GTT table base register format
* _____________________________________________
* Bits Description |
* 0 GTT table enable bit |
* 11:1 reserved |
* 31:12 physical addr 31:12 |
* ---------------------------------------------
*/
/* Intel agp bridge specific */
/* Amd64 cpu gart device reigster offset */
/* Amd64 cpu gart bits */
/* Other common routines */
#endif /* _KERNEL */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_AGPDEFS_H */