/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Provides access macros and routines to the OpenHCI HW.
*/
#ifdef __cplusplus
extern "C" {
#endif
/* Misc */
/* OpenHCI Global Swap location in PCI space */
/* PHY Register #1 */
/* PHY Register #4 */
/* PHY Register #4 */
/* PHY Register #5 */
/* OpenHCI Event Codes. Refer to OHCI 1.0 section 3.1.1 */
/* hci_regs_s.ir_ctxt_regs.ctxt_match */
#define OHCI_MTC_CHAN_SHIFT 0
/* hci_regs_s.self_id_buflo - See OpenHCI 1.00 section 11.1 */
/* hci_regs_s.self_id_count - See OpenHCI 1.00 section 11.2 */
/*
* hci_regs_s.int_event_* and hci_regs_s.int_mask_*
* See OpenHCI 1.00 section 6
*/
/* hci_regs_s.fairness_ctrl - See OpenHCI 1.00 section 5.8 */
/* hci_regs_s.link_ctrl_set/clr - See OpenHCI 1.00 section 5.9 */
/* Defines for registers in HCI register space */
/* hci_regs_s.version - See OpenHCI 1.00 section 5.2 */
/* hci_regs_s.guid_rom - See OpenHCI 1.00 section 5.3 */
/* hci_regs_s.at_retries - See OpenHCI 1.00 section 5.4 */
#define OHCI_RET_MAX_ATREQ_SHIFT 0
/* hci_regs_s.csr_ctrl - See OpenHCI 1.00 section 5.5.1 */
/* hci_regs_s.config_rom_hdr - See OpenHCI 1.00 section 5.5.6 */
/* hci_regs_s.bus_options - See OpenHCI 1.00 section 5.5.4 */
/* hci_regs_s.guid_hi - See OpenHCI 1.00 section 5.5.5 */
/* hci_regs_s.config_rom_maplo - See OpenHCI 1.00 section 5.5.6 */
/* hci_regs_s.posted_write_addrhi - See OpenHCI 1.00 section 13.2.8.1 */
/* hci_regs_s.vendor_id - See OpenHCI 1.00 section 5.2 */
/* hci_regs_s.hc_ctrl_set/clr - See OpenHCI 1.00 section 5.7 */
/* hci_regs_s.node_id - See OpenHCI 1.00 section 5.10 */
#define OHCI_NDID_NODENUM_SHIFT 0
/* hci_regs_s.phy_ctrl - See OpenHCI 1.00 section 5.11, 1394-1994 J.4.1 */
#define OHCI_PHYC_WRDATA_SHIFT 0
/* hci_regs_s.context_ctrl -- several contexts */
#define OHCI_CC_EVT_SHIFT 0
/* hci_regs context_ctrl for IR */
/* hci_regs context_ctrl for IT */
((tcode == IEEE1394_TCODE_WRITE_RESP) || \
(tcode == IEEE1394_TCODE_READ_QUADLET_RESP) || \
(tcode == IEEE1394_TCODE_READ_BLOCK_RESP) || \
((tcode == IEEE1394_TCODE_READ_QUADLET) || \
(tcode == IEEE1394_TCODE_WRITE_QUADLET) || \
(tcode == IEEE1394_TCODE_READ_BLOCK) || \
(tcode == IEEE1394_TCODE_WRITE_BLOCK) || \
(tcode == IEEE1394_TCODE_LOCK) || \
(tcode == IEEE1394_TCODE_PHY))
(((MATCHENBL) << OHCI_IRCTL_MTC_ENBL_SHIFT) & \
(((MATCHENBL) << OHCI_IRCTL_MTC_ENBL_SHIFT) & \
(((MATCHENBL) << OHCI_ITCTL_MTC_ENBL_SHIFT) & \
(((MATCHENBL) << OHCI_ITCTL_MTC_ENBL_SHIFT) & \
/*
* 1394 OpenHCI 1.0 general context register layout
* All contexts except for Isoch Receive have the following layout
* See the OpenHCI v1.0 specification for register definitions.
*/
typedef struct hci1394_ctxt_regs_s {
/*
* 1394 OpenHCI 1.0 Isochronous Receive context register layout
* See the OpenHCI v1.0 specification for register definitions.
*/
typedef struct hci1394_ir_ctxt_regs_s {
/*
* 1394 OpenHCI 1.0 registers
* See the OpenHCI v1.0 specification for register definitions.
*/
typedef struct hci1394_regs_s {
/* private structure to keep track of OpenHCI */
typedef struct hci1394_ohci_s {
/* config ROM and selfid buffers */
/*
* Phy register #1 cached settings. These are only used for 1394-1995
* phy's. When setting the root holdoff bit and gap count in 1394,
* you send out a PHY configuration packet. The 1995 PHY's will
* not look at the PHY packet if we sent it out which means we have
* to write directly to PHY register 1. This creates some ugly race
* conditions. Since we will be following up these settings with a bus
* reset shortly, we "cache" them until we generate the bus reset. This
* solution is not perfect, but it is the best of a bad thing.
*/
/*
* The bus time is kept using the cycle timer and then counting the
* rollovers via the cycle 64 seconds interrupt. (NOTE: every 2
* interrupts is one rollover) We do not wish to be interrupting
* the CPU if there is nothing plugged into the bus (since bus time
* really isn't used for anything yet (maybe when bridges come out?)).
* We will start with the interrupt disabled, if the bus master writes
* to the CSR bus time register, we will enable the interrupt. These
* fields keep track of the rollover and whether or not the interrupt
* is enabled.
*/
/* whether we have a 1394-1995 or 1394A phy */
/* General Driver Info */
/*
* self id buffer and config rom info. These are towards bottom of the
* structure to make debugging easier.
*/
/* OpenHCI registers */
/*
* This mutex is used to protect "atomic" operations to the OpenHCI
* hardware. This includes reads and writes to the PHY, cswap
* write operations such as updating atreq retries.
*/
/* handle passed back from init() and used for rest of functions */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_1394_ADAPTERS_HCI1394_OHCI_H */