xgehal-regs.h revision a23fd118e437af0a7877dd313db8fdaa3537c675
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
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*/
/*
* Copyright (c) 2002-2005 Neterion, Inc.
* All right Reserved.
*
* FileName : xgehal-regs.h
*
* Description: Xframe mem-mapped register space
*
* Created: 14 May 2004
*/
#ifndef XGE_HAL_REGS_H
#define XGE_HAL_REGS_H
typedef struct {
/* General Control-Status Registers */
#define XGE_HAL_GEN_INTR_TXPIC BIT(0)
#define XGE_HAL_GEN_ERROR_INTR (XGE_HAL_GEN_INTR_TXPIC | \
/* XGXS must be removed from reset only once. */
#define XGE_HAL_SW_RESET_ALL (XGE_HAL_SW_RESET_XENA | \
/* The SW_RESET register must read this value after a successful reset. */
#if defined(XGE_OS_HOST_BIG_ENDIAN) && !defined(XGE_OS_PIO_LITTLE_ENDIAN)
#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA500000000ULL
#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A500000000ULL
#else
#define XGE_HAL_SW_RESET_RAW_VAL_XENA 0xA5000000ULL
#define XGE_HAL_SW_RESET_RAW_VAL_HERC 0xA5A50000ULL
#endif
#define XGE_HAL_ADAPTER_STATUS_TDMA_READY BIT(0)
#define XGE_HAL_SERR_SOURCE_PIC BIT(0)
#define XGE_HAL_SERR_SOURCE_ANY (XGE_HAL_SERR_SOURCE_PIC | \
/* PCI-X Controller registers */
#define XGE_HAL_PIC_INT_TX BIT(0)
#define XGE_HAL_PCIX_INT_REG_ECC_SG_ERR BIT(0)
/*
#define XGE_HAL_PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
#define XGE_HAL_PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
#define XGE_HAL_PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
*/
#define XGE_HAL_RX_PIC_INT_REG_SPDM_READY BIT(0)
#define XGE_HAL_MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
#define XGE_HAL_MISC_INT_REG_DP_ERR_INT BIT(0)
#define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n)
#define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n)
/* PIC Control registers */
#define XGE_HAL_PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
#define XGE_HAL_SWAPPER_CTRL_PIF_R_FE BIT(0)
#define XGE_HAL_IF_RD_SWAPPER_FB 0x0123456789ABCDEFULL
#define XGE_HAL_SCHED_INT_CTRL_TIMER_EN BIT(0)
#define XGE_HAL_SCHED_INT_PERIOD_MASK 0xFFFFFFFF00000000ULL
#define XGE_HAL_STATREQTO_VAL(n) TBD
#define XGE_HAL_XMSI_EN BIT(0)
/* Automated statistics collection */
#define XGE_HAL_STAT_CFG_STAT_EN BIT(0)
#define XGE_HAL_XENA_PER_SEC 0x208d5
/* General Configuration */
#define XGE_HAL_SPDM_PCI_BAR_NUM(spdm_bir_offset) \
#define XGE_HAL_SPDM_PCI_BAR_OFFSET(spdm_bir_offset) \
#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \
#define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \
#define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \
/* TxDMA registers */
#define XGE_HAL_TXDMA_PFC_INT BIT(0)
/* TxDMA arbiter */
/* Tx FIFO controller */
#define XGE_HAL_X_MAX_FIFOS 8
#define XGE_HAL_TX_FIFO_PARTITION_EN BIT(0)
#define XGE_HAL_TX_FIFO_PARTITION_PRI_0 0 /* highest */
#define XGE_HAL_TX_FIFO_PARTITION_PRI_1 1
#define XGE_HAL_TX_FIFO_PARTITION_PRI_2 2
#define XGE_HAL_TX_FIFO_PARTITION_PRI_3 3
#define XGE_HAL_TX_FIFO_PARTITION_PRI_4 4
#define XGE_HAL_TX_FIFO_PARTITION_PRI_5 5
#define XGE_HAL_TX_FIFO_PARTITION_PRI_6 6
/* Tx Protocol assist */
/* Recent add, used only debug purposes. */
/* RxDMA Registers */
#define XGE_HAL_RXDMA_RC_INT BIT(0)
#define XGE_HAL_RXDMA_INT_RC_INT_M BIT(0)
/* DMA arbiter */
#define XGE_HAL_RX_QUEUE_PRI_0 0 /* highest */
#define XGE_HAL_RX_QUEUE_PRI_1 1
#define XGE_HAL_RX_QUEUE_PRI_2 2
#define XGE_HAL_RX_QUEUE_PRI_3 3
#define XGE_HAL_RX_QUEUE_PRI_4 4
#define XGE_HAL_RX_QUEUE_PRI_5 5
#define XGE_HAL_RX_QUEUE_PRI_6 6
/* Per-ring controller regs */
#define XGE_HAL_RX_MAX_RINGS 8
/* Receive traffic interrupts */
/* Media Access Controller Register */
#define XGE_HAL_MAC_INT_STATUS_TMAC_INT BIT(0)
#define XGE_HAL_RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
#define XGE_HAL_MAC_CFG_TMAC_ENABLE BIT(0)
#define XGE_HAL_RMAC_ERR_FCS BIT(0)
#define XGE_HAL_MAX_MAC_ADDRESSES 64
pkts */
#define XGE_HAL_RMAC_ADDR_CMD_MEM_RD 0
/*
u64 rmac_addr_cfg;
#define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
#define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
#define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48
#define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
*/
#define XGE_HAL_RMAC_PAUSE_GEN_EN BIT(0)
/* rx traffic steering */
#define XGE_HAL_MAX_DIX_MAP 4
#define XGE_HAL_RTS_MAC_SECT0_EN BIT(0)
#define XGE_HAL_MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
/* memory controller registers */
#define XGE_HAL_MC_INT_STATUS_MC_INT BIT(0)
#define XGE_HAL_MC_INT_MASK_MC_INT BIT(0)
/* MC configuration */
/* XGXG */
/* XGXS control registers */
#define XGE_HAL_XGXS_INT_STATUS_TXGXS BIT(0)
#define XGE_HAL_XGXS_INT_MASK_TXGXS BIT(0)
/* Using this strcture to calculate offsets */
typedef struct xge_hal_pci_config_le_t {
} xge_hal_pci_config_le_t; // 0x100
typedef struct xge_hal_pci_config_t {
#ifdef XGE_OS_HOST_BIG_ENDIAN
#else
#endif
} xge_hal_pci_config_t; // 0x100
#define XGE_HAL_REG_SPACE sizeof(xge_hal_pci_bar0_t)
#endif /* XGE_HAL_REGS_H */