/*
* Copyright (c) 2008-2016 Solarflare Communications Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing official
* policies, either expressed or implied, of the FreeBSD Project.
*/
/* PCIe 3.0 link speeds */
#ifndef PCIE_LINKCAP_MAX_SPEED_5
#endif
#ifndef PCIE_LINKSTS_SPEED_5
#endif
#ifndef PCIE_LINKCAP_MAX_SPEED_8
#endif
#ifndef PCIE_LINKSTS_SPEED_8
#endif
#include "sfxge.h"
int
{
int rc;
if (!(stat & PCI_STAT_CAP)) {
goto fail1;
}
off + PCI_CAP_ID))
goto done;
}
goto fail2;
done:
return (0);
return (rc);
}
int
{
int rc;
int *pci_regs;
/*
* We need the PCI bus address to format MCDI logging output in the
* same way as on other platforms.
* It appears there's no straightforward way to extract the address
* from a "dev_info_t" structure, though.
* The "reg" property is supported by all PCIe devices, and contains
* an arbitrary length array of elements describing logical
* resources. Each element contains a 5-tuple of 32bit values,
* information.
*/
goto fail1;
}
#endif
goto fail1;
}
goto fail2;
goto fail3;
switch (linksts & PCIE_LINKSTS_NEG_WIDTH_MASK) {
break;
break;
break;
break;
default:
break;
}
switch (linksts & PCIE_LINKSTS_SPEED_MASK) {
case PCIE_LINKSTS_SPEED_2_5:
break;
case PCIE_LINKSTS_SPEED_5:
break;
case PCIE_LINKSTS_SPEED_8:
break;
default:
break;
}
SFXGE_CMN_ERR "PCIe MRR: %d TLP: %d Link: %s Lanes: x%d",
128 << max_read_request,
128 << max_payload_size,
"UNKNOWN",
sp->s_pcie_nlanes);
return (0);
return (rc);
}
void
unsigned int full_speed)
{
SFXGE_CMN_ERR "This device requires %d PCIe lanes "
"at %s link speed to reach full bandwidth.",
"UNKNOWN");
}
void
{
sp->s_pcie_nlanes = 0;
sp->s_pcie_linkspeed = 0;
}