/*
* Copyright (c) 2007-2015 Solarflare Communications Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing official
* policies, either expressed or implied, of the FreeBSD Project.
*/
#ifndef _SYS_EFX_EF10_REGS_H
#define _SYS_EFX_EF10_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
/**************************************************************************
* NOTE: the line below marks the start of the autogenerated section
* EF10 registers and descriptors
*
**************************************************************************
*/
/*
* BIU_HW_REV_ID_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_HW_REV_ID_LBN 0
/*
* BIU_MC_SFT_STATUS_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_MC_SFT_STATUS_LBN 0
/*
* BIU_INT_ISR_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_ISR_REG_LBN 0
/*
* MC_DB_LWRD_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_MC_DOORBELL_L_LBN 0
/*
* MC_DB_HWRD_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_MC_DOORBELL_H_LBN 0
/*
* EVQ_RPTR_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_EVQ_RPTR_LBN 0
/*
* EVQ_TMR_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_TC_TIMER_VAL_LBN 0
/*
* RX_DESC_UPD_REG(32bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_RX_DESC_WPTR_LBN 0
/*
* TX_DESC_UPD_REG(96bit):
*
*/
/* hunta0,medforda0=pcie_pf_bar2 */
#define ERF_DZ_TX_DESC_LWORD_LBN 0
/* ES_DRIVER_EV */
#define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0
#define ESF_DZ_DRV_SUB_DATA_LBN 0
#define ESF_DZ_DRV_EVQ_ID_LBN 0
#define ESF_DZ_DRV_TMR_ID_LBN 0
/* ES_EVENT_ENTRY */
#define ESE_DZ_EV_CODE_RX_EV 0
#define ESF_DZ_EV_DATA_DW0_LBN 0
#define ESF_DZ_EV_DATA_LBN 0
/* ES_MC_EVENT */
#define ESF_DZ_MC_SOFT_DW0_LBN 0
#define ESF_DZ_MC_SOFT_LBN 0
/* ES_RX_EVENT */
#define ESE_DZ_L4_CLASS_UNKNOWN 0
#define ESE_DZ_L3_CLASS_UNKNOWN 0
#define ESE_DZ_ETH_TAG_CLASS_NONE 0
#define ESE_DZ_ETH_BASE_CLASS_ETH2 0
#define ESE_DZ_MAC_CLASS_UCAST 0
#define ESE_EZ_ENCAP_HDR_NONE 0
#define ESF_DZ_RX_BYTES_LBN 0
/* ES_RX_KER_DESC */
#define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0
#define ESF_DZ_RX_KER_BUF_ADDR_LBN 0
/* ES_TX_CSUM_TSTAMP_DESC */
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESE_DZ_TX_OPTION_CRC_OFF 0
#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
/* ES_TX_EVENT */
#define ESF_DZ_TX_DESCR_INDX_LBN 0
/* ES_TX_KER_DESC */
#define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0
#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0
/* ES_TX_PIO_DESC */
#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
/* ES_TX_TSO_DESC */
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
/* TX_TSO_FATSO2A_DESC */
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
/* TX_TSO_FATSO2B_DESC */
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
#define ESF_DZ_TX_TSO_INNER_PE_CSUM_LBN 0
/* ES_TX_VLAN_DESC */
#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
#define ESF_DZ_TX_VLAN_TAG1_LBN 0
/*************************************************************************
* NOTE: the comment line above marks the end of the autogenerated section
*/
/*
* The workaround for bug 35388 requires multiplexing writes through
* the ERF_DZ_TX_DESC_WPTR address.
* TX_DESC_UPD: 0ppppppppppp (bit 11 lost)
* EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits)
* EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost)
*/
#define ERF_DD_EVQ_IND_RPTR_LBN 0
#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0
#ifdef __cplusplus
}
#endif
#endif /* _SYS_EFX_EF10_REGS_H */