/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2007, 2008
* Damien Bergamini <damien.bergamini@free.fr>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RT2860_REG_H
#define _RT2860_REG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Device ID */
/* PCI registers */
/* PBF registers */
/* MAC registers */
/* undocumented registers */
/* MAC Timing control registers */
/* MAC Power Save configuration registers */
/* MAC TX configuration registers */
/* MAC RX configuration registers */
/* MAC Security configuration registers */
/* MAC Statistics Counters */
/* RX WCID search table */
/* Pair-wise key table */
/* WCID attribute table */
/* Shared Key Table */
/* Shared Key Mode */
/* Shared Memory between MCU and host */
/* possible flags for register RT2860_PCI_EECTRL */
/* possible flags for registers INT_STATUS/INT_MASK */
/* possible flags for register WPDMA_GLO_CFG */
#define RT2860_WPDMA_BT_SIZE16 0
/* possible flags for register DELAY_INT_CFG */
#define RT2860_RXMAX_PTIME_SHIFT 0
/* possible flags for register GPIO_CTRL */
#define RT2860_GPIO_O_SHIFT 0
/* possible flags for register US_CYC_CNT */
#define RT2860_US_CYC_CNT_SHIFT 0
/* possible flags for register SYS_CTRL */
/* possible values for register HOST_CMD */
/* possible flags for register PBF_CFG */
/* possible flags for register BUF_CTRL */
/* possible flags for registers MCU_INT_STA/MCU_INT_ENA */
/* possible flags for register CAP_CTRL */
#define RT2860_START_ADDR_SHIFT 0
/* possible flags for register MAC_SYS_CTRL */
/* possible flags for register MAC_BSSID_DW1 */
/* possible flags for register MAX_LEN_CFG */
#define RT2860_MAX_PSDU_LEN8K 0
#define RT2860_MAX_MPDU_LEN_SHIFT 0
/* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */
#define RT2860_BBP_DATA_SHIFT 0
/* possible flags for register RF_CSR_CFG0 */
#define RT2860_RF_REG_0_SHIFT 0
/* possible flags for register RF_CSR_CFG1 */
#define RT2860_RF_REG_1_SHIFT 0
/* possible flags for register LED_CFG */
#define RT2860_LED_MODE_OFF 0
#define RT2860_LED_ON_TIME_SHIFT 0
/* possible flags for register XIFS_TIME_CFG */
#define RT2860_CCK_SIFS_TIME_SHIFT 0
/* possible flags for register BKOFF_SLOT_CFG */
#define RT2860_SLOT_TIME 0
/* possible flags for register NAV_TIME_CFG */
#define RT2860_NAV_TIMER_SHIFT 0
/* possible flags for register CH_TIME_CFG */
/* possible values for register BCN_TIME_CFG */
#define RT2860_TSF_SYNC_MODE_DIS 0
#define RT2860_BCN_INTVAL_SHIFT 0
/* possible flags for register TBTT_SYNC_CFG */
#define RT2860_TBTT_ADJUST_SHIFT 0
/* possible flags for register INT_TIMER_CFG */
#define RT2860_PRE_TBTT_TIMER_SHIFT 0
/* possible flags for register INT_TIMER_EN */
/* possible flags for register MAC_STATUS_REG */
/* possible flags for register PWR_PIN_CFG */
/* possible flags for register AUTO_WAKEUP_CFG */
#define RT2860_WAKEUP_LEAD_TIME_SHIFT 0
/* possible flags for register TX_PIN_CFG */
/* possible flags for register TX_BAND_CFG */
/* possible flags for register TX_SW_CFG0 */
#define RT2860_DLY_TXPE_EN_SHIFT 0
/* possible flags for register TX_SW_CFG1 */
/* possible flags for register TX_SW_CFG2 */
#define RT2860_DLY_DAC_DIS_SHIFT 0
/* possible flags for register TXOP_THRES_CFG */
#define RT2860_RDG_OUT_THRES 0
/* possible flags for register TXOP_CTRL_CFG */
/* possible flags for register TX_RTS_CFG */
#define RT2860_RTS_RTY_LIMIT_SHIFT 0
/* possible flags for register TX_TIMEOUT_CFG */
/* possible flags for register TX_RTY_CFG */
#define RT2860_SHORT_RTY_LIMIT_SHIFT 0
/* possible flags for register TX_LINK_CFG */
#define RT2860_REMOTE_MFB_LT_SHIFT 0
/* possible flags for registers *_PROT_CFG */
/* possible flags for registers EXP_{CTS,ACK}_TIME */
#define RT2860_EXP_CCK_TIME_SHIFT 0
/* possible flags for register RX_FILTR_CFG */
/* possible flags for register AUTO_RSP_CFG */
/* possible flags for register SIFS_COST_CFG */
#define RT2860_CCK_SIFS_COST_SHIFT 0
/* possible flags for register TXOP_HLDR_ET */
/* possible flags for register TX_STAT_FIFO */
/* possible flags for register WCID_ATTR */
#define RT2860_MODE_NOSEC 0
/* possible flags for register H2M_MAILBOX */
/* possible flags for MCU command RT2860_MCU_CMD_LEDS */
#pragma pack(1)
/* TX descriptor */
struct rt2860_txd {
};
#pragma pack()
#pragma pack(1)
/* TX Wireless Information */
struct rt2860_txwi {
#define RT2860_TX_TXOP_HT 0
};
#pragma pack()
#pragma pack(1)
/* RX descriptor */
struct rt2860_rxd {
};
#pragma pack()
#pragma pack(1)
/* RX Wireless Information */
struct rt2860_rxwi {
};
#pragma pack()
#define RAL_RF1 0
/*
* control and status registers access macros
*/
/*
* EEPROM access macro
*/
}
/*
* Default values for MAC registers; values taken from the reference driver.
*/
#define RT2860_DEF_MAC \
{ RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \
{ RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \
{ RT2860_HT_BASIC_RATE, 0x00008003 }, \
{ RT2860_MAC_SYS_CTRL, 0x00000000 }, \
{ RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \
{ RT2860_TX_SW_CFG0, 0x00040a06 }, \
{ RT2860_TX_SW_CFG1, 0x00080606 }, \
{ RT2860_TX_LINK_CFG, 0x00001020 }, \
{ RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \
{ RT2860_LED_CFG, 0x7f031e46 }, \
{ RT2860_WMM_AIFSN_CFG, 0x00002273 }, \
{ RT2860_WMM_CWMIN_CFG, 0x00002344 }, \
{ RT2860_WMM_CWMAX_CFG, 0x000034aa }, \
{ RT2860_MAX_PCNT, 0x1f3fbf9f }, \
{ RT2860_TX_RTY_CFG, 0x47d01f0f }, \
{ RT2860_AUTO_RSP_CFG, 0x00000013 }, \
{ RT2860_CCK_PROT_CFG, 0x05740003 }, \
{ RT2860_OFDM_PROT_CFG, 0x05740003 }, \
{ RT2860_GF20_PROT_CFG, 0x01744004 }, \
{ RT2860_GF40_PROT_CFG, 0x03f44084 }, \
{ RT2860_MM20_PROT_CFG, 0x01744004 }, \
{ RT2860_MM40_PROT_CFG, 0x03f54084 }, \
{ RT2860_TXOP_CTRL_CFG, 0x0000583f }, \
{ RT2860_TXOP_HLDR_ET, 0x00000002 }, \
{ RT2860_TX_RTS_CFG, 0x00092b20 }, \
{ RT2860_EXP_ACK_TIME, 0x002400ca }, \
{ RT2860_XIFS_TIME_CFG, 0x33a41010 }, \
{ RT2860_PWR_PIN_CFG, 0x00000003 }
/*
* Default values for BBP registers; values taken from the reference driver.
*/
#define RT2860_DEF_BBP \
{ 65, 0x2c }, \
{ 66, 0x38 }, \
{ 69, 0x12 }, \
{ 73, 0x10 }, \
{ 81, 0x37 }, \
{ 82, 0x62 }, \
{ 83, 0x6a }, \
{ 84, 0x19 }, \
{ 86, 0x00 }, \
{ 91, 0x04 }, \
{ 92, 0x00 }, \
{ 105, 0x01 }
/*
* Default settings for RF registers; values derived from the reference driver.
*/
#define RT2860_RF2850 \
{ 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \
{ 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \
{ 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \
{ 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \
{ 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \
{ 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \
{ 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \
{ 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \
{ 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \
{ 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \
{ 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \
{ 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \
{ 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \
{ 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \
{ 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \
{ 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \
{ 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \
{ 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \
{ 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \
{ 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \
{ 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \
{ 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \
{ 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \
{ 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \
{ 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \
{ 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \
{ 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \
{ 102, 0x100bb2, 0x1301ac, 0x05e014, 0x001404 }, \
{ 104, 0x100bb2, 0x1301ac, 0x05e014, 0x001408 }, \
{ 108, 0x100bb3, 0x13028c, 0x05e014, 0x001404 }, \
{ 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \
{ 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \
{ 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \
{ 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \
{ 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \
{ 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \
{ 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \
{ 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \
{ 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \
{ 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \
{ 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \
{ 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \
{ 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \
{ 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \
{ 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \
{ 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \
{ 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \
{ 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \
{ 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }
#ifdef __cplusplus
}
#endif
#endif /* _RT2860_REG_H */