/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2006
* Damien Bergamini <damien.bergamini@free.fr>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _RT2661_REG_H
#define _RT2661_REG_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Control and status registers.
*/
/* possible flags for register HOST_CMD_CSR */
/* Host to MCU (8051) command identifiers */
/* possible flags for register MCU_CNTL_CSR */
/* possible flags for register MCU_INT_SOURCE_CSR */
/* possible flags for register H2M_MAILBOX_CSR */
/* possible flags for register MAC_CSR5 */
/* possible flags for register TXRX_CSR0 */
/* Tx filter flags are in the low 16 bits */
/* Rx filter flags are in the high 16 bits */
/* possible flags for register TXRX_CSR4 */
/* possible flags for register TXRX_CSR9 */
/* TBTT stands for Target Beacon Transmission Time */
/* possible flags for register PHY_CSR0 */
/* possible flags for register PHY_CSR3 */
/* possible flags for register PHY_CSR4 */
/* possible values for register STA_CSR4 */
#define RT2661_TX_SUCCESS 0
/* possible flags for register TX_CNTL_CSR */
/* possible flags for register INT_SOURCE_CSR */
/* possible flags for register E2PROM_CSR */
#pragma pack(1)
/* Tx descriptor */
struct rt2661_tx_desc {
#define RT2661_QID(v) (v)
#define RT2661_DEFAULT_TXPOWER 0
};
#pragma pack()
#pragma pack(1)
/* Rx descriptor */
struct rt2661_rx_desc {
};
#pragma pack()
#define RT2661_RF1 0
/* dual-band RF */
/* single-band RF */
/*
* control and status registers access macros
*/
/*
* EEPROM access macro
*/
} while (0)
/*
* Default values for MAC registers; values taken from the reference driver.
*/
#define RT2661_DEF_MAC \
{ RT2661_TXRX_CSR0, 0x0000b032 }, \
{ RT2661_TXRX_CSR1, 0x9eb39eb3 }, \
{ RT2661_TXRX_CSR2, 0x8a8b8c8d }, \
{ RT2661_TXRX_CSR3, 0x00858687 }, \
{ RT2661_TXRX_CSR7, 0x2e31353b }, \
{ RT2661_TXRX_CSR8, 0x2a2a2a2c }, \
{ RT2661_TXRX_CSR15, 0x0000000f }, \
{ RT2661_MAC_CSR6, 0x00000fff }, \
{ RT2661_MAC_CSR8, 0x016c030a }, \
{ RT2661_MAC_CSR10, 0x00000718 }, \
{ RT2661_MAC_CSR12, 0x00000004 }, \
{ RT2661_MAC_CSR13, 0x0000e000 }, \
{ RT2661_SEC_CSR0, 0x00000000 }, \
{ RT2661_SEC_CSR1, 0x00000000 }, \
{ RT2661_SEC_CSR5, 0x00000000 }, \
{ RT2661_PHY_CSR1, 0x000023b0 }, \
{ RT2661_PHY_CSR5, 0x060a100c }, \
{ RT2661_PHY_CSR6, 0x00080606 }, \
{ RT2661_PHY_CSR7, 0x00000a08 }, \
{ RT2661_PCI_CFG_CSR, 0x3cca4808 }, \
{ RT2661_AIFSN_CSR, 0x00002273 }, \
{ RT2661_CWMIN_CSR, 0x00002344 }, \
{ RT2661_CWMAX_CSR, 0x000034aa }, \
{ RT2661_TEST_MODE_CSR, 0x00000200 }, \
{ RT2661_M2H_CMD_DONE_CSR, 0xffffffff }
/*
* Default values for BBP registers; values taken from the reference driver.
*/
#define RT2661_DEF_BBP \
{ 3, 0x00 }, \
{ 15, 0x30 }, \
{ 17, 0x20 }, \
{ 21, 0xc8 }, \
{ 22, 0x38 }, \
{ 23, 0x06 }, \
{ 24, 0xfe }, \
{ 25, 0x0a }, \
{ 26, 0x0d }, \
{ 34, 0x12 }, \
{ 37, 0x07 }, \
{ 39, 0xf8 }, \
{ 41, 0x60 }, \
{ 53, 0x10 }, \
{ 54, 0x18 }, \
{ 60, 0x10 }, \
{ 61, 0x04 }, \
{ 62, 0x04 }, \
{ 75, 0xfe }, \
{ 86, 0xfe }, \
{ 88, 0xfe }, \
{ 90, 0x0f }, \
{ 99, 0x00 }, \
{ 102, 0x16 }, \
{ 107, 0x04 }
/*
* Default settings for RF registers; values taken from the reference driver.
*/
#define RT2661_RF5225_1 \
{ 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
{ 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
{ 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
{ 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
{ 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
{ 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
{ 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
{ 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
{ 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
{ 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
{ 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
{ 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
{ 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
{ 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
\
{ 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \
{ 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \
{ 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \
{ 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \
{ 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \
{ 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \
{ 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \
{ 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \
\
{ 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \
{ 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \
{ 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \
{ 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \
{ 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \
{ 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \
{ 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \
{ 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \
{ 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \
{ 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \
{ 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \
\
{ 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \
{ 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \
{ 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \
{ 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \
{ 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
#define RT2661_RF5225_2 \
{ 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
{ 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
{ 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
{ 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
{ 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
{ 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
{ 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
{ 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
{ 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
{ 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
{ 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
{ 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
{ 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
{ 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
\
{ 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \
{ 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \
{ 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \
{ 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \
{ 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \
{ 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \
{ 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \
{ 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \
\
{ 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \
{ 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \
{ 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \
{ 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \
{ 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \
{ 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \
{ 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \
{ 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \
{ 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \
{ 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \
{ 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \
\
{ 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \
{ 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \
{ 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \
{ 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \
{ 165, 0x00b35, 0x11246, 0x2e014, 0x30285 }
#ifdef __cplusplus
}
#endif
#endif /* _RT2661_REG_H */