/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2004, 2005 David Young. All rights reserved.
*
* Programmed for NetBSD by David Young.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* 3. The name of David Young may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
* Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/* Macros for bit twiddling. */
#ifndef _RTW_REG_H_
#define _RTW_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _BIT_TWIDDLE
#define _BIT_TWIDDLE
/*
* nth bit, BIT(0) == 0x1.
*/
/*
* bits m through n, m < n.
*/
/*
* find least significant bit that is set
*/
/*
* for x a power of two and p a non-negative integer, is x a greater
* power than 2**p?
*/
#define MASK_TO_SHIFT4(m) \
: MASK_TO_SHIFT2((m)))
#define MASK_TO_SHIFT8(m) \
: MASK_TO_SHIFT4((m)))
#define MASK_TO_SHIFT16(m) \
: MASK_TO_SHIFT8((m)))
#define MASK_TO_SHIFT(m) \
: MASK_TO_SHIFT16((m)))
#endif /* _BIT_TWIDDLE */
/* RTL8180L Host Control and Status Registers */
/*
* ID Register: MAC addr, 6 bytes.
* Auto-loaded from EEPROM. Read by byte, by word, or by double word,
* but write only by double word.
*/
/*
* Timing Synchronization Function Timer Register,
* low word, 32b, read-only.
*/
/*
* Transmit Low Priority Descriptors Start Address,
* 32b, 256-byte alignment.
*/
/*
* Transmit Normal Priority Descriptors Start Address,
* 32b, 256-byte alignment.
*/
/*
* Transmit High Priority Descriptors Start Address,
* 32b, 256-byte alignment.
*/
/*
* 0: use long PLCP header
*/
/*
* 8181 and 8180 docs conflict!
*/
/*
* BSSID, 6 bytes
*/
/*
* Reset: host sets to 1 to disable
* transmitter & receiver, reinitialize FIFO.
* RTL8180L sets to 0 to signal completion.
*/
/*
* Receiver Enable: host enables receiver
* by writing 1. RTL8180L indicates receiver
* is active with 1. After power-up, host
* must wait for reset before writing.
*/
/*
* Transmitter Enable: host enables transmitter
* by writing 1. RTL8180L indicates transmitter
* is active with 1. After power-up, host
* must wait for reset before writing.
*/
/*
* 1 enables,
* 0 disables. XXX RTL8180, only?
*/
/*
* Time Out: 1 indicates RTW_TSFTR[0:31] = RTW_TINT
*/
/*
* Beacon Time Out: time for host to prepare beacon:
* RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
* (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV)
*/
/*
* ATIM Time Out: ATIM interval will pass,
* RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
* (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV)
*/
/*
* Tx Beacon Descriptor Error:
* beacon transmission aborted because
* frame Rx'd
*/
/*
* Tx High Priority Descriptor Error:
*/
/*
* Tx Normal Priority Descriptor Error:
*/
/*
* Rx FIFO Overflow: either RDU (see below)
*/
/*
* Tx Low Priority Descriptor Error
*/
/*
* Convenient interrupt conjunctions.
*/
/*
* 1: host assigns 802.11 sequence number,
* 0: hardware assigns sequence number
*/
/* Hardware version ID, read-only */
/*
* 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
* 0: ACK rate = 1Mbps
*/
/* Max DMA Burst Size per Tx DMA Burst */
/*
* host lets RTL8180 append ICV to WEP packets
*/
/*
*/
/*
* 0: RTL8180 appends CRC32
* 1: host appends CRC32
*
* (I *think* this is right. The docs have a mysterious
* description in the passive voice.)
*/
/*
* only do Early Rx on packets longer than 1536 bytes
*/
/*
* according to RTW_MSR_NETYPE.
*/
/*
* when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept
*/
/*
* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
* bytes are received
*/
/*
* Max DMA Burst Size per Rx DMA Burst
*/
/*
* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46
*/
/*
* accept physical match frames. XXX means PLCP header ok?
*/
/*
* Additional bits to set in monitor mode.
*/
#define RTW_RCR_MONITOR ( \
RTW_RCR_AAP | \
RTW_RCR_ACF | \
RTW_RCR_ACRC32 | \
RTW_RCR_AICV | \
0)
/*
* The packet filter bits.
*/
#define RTW_RCR_PKTFILTER_MASK (\
RTW_RCR_AAP | \
RTW_RCR_AB | \
RTW_RCR_ACF | \
RTW_RCR_ACRC32 | \
RTW_RCR_ADD3 | \
RTW_RCR_ADF | \
RTW_RCR_AICV | \
RTW_RCR_AM | \
RTW_RCR_AMF | \
RTW_RCR_APM | \
RTW_RCR_APWRMGT | \
0)
/*
*/
#define RTW_RCR_PKTFILTER_DEFAULT ( \
RTW_RCR_ENCS1 | \
RTW_RCR_CBSSID | \
RTW_RCR_ADF | \
RTW_RCR_AMF | \
RTW_RCR_APM | \
RTW_RCR_AM | \
RTW_RCR_AB | \
0)
#define RTW_RCR_PROMIC ( \
RTW_RCR_AAP | \
0)
/*
* Transmit Beacon Descriptor Start Address,
* 32b, 256-byte alignment
*/
/*
* Load the EEPROM. Reset registers to defaults.
* Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL.
* XXX RTL8180 only?
*/
/*
* Disable network & bus-master operations and enable
* _EECS, _EESK, _EEDI, _EEDO.
* XXX RTL8180 only?
*/
/* Enable RTW_CONFIG[0123] registers. */
/*
* XXX RTL8180 only?
*/
/*
* implements 40-bit WEP, XXX RTL8180 only?
*/
/*
* implements 104-bit WEP, from EEPROM, read-only XXX RTL8180 only?
*/
/*
* 1: RTW_PSR_LEDGPO[01] control LED[01] pins.
* 0: LED behavior defined by RTW_CONFIG1_LEDS10_MASK
* XXX RTL8180 only?
*/
/*
* auxiliary power is present, read-only
*/
/*
* Geographic Location, read-only
*/
/*
* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_*
* work.
*/
/*
* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0.
*/
/*
*
* Setting LED0 LED1
* ------- ---- ----
* RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure
* RTW_CONFIG1_LEDS_ACT_LINK Activity Link
* RTW_CONFIG1_LEDS_TX_RX Tx Rx
*/
/*
* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms.
*
* RTW_CONFIG1_LWACT
* 0 1
* RTW_CONFIG4_LWPTN 0 active high active low
* 1 positive pulse negative pulse
*/
/*
* if set, VPD from offsets 0x40-0x7f in EEPROM are at
* registers 0x60-0x67 of PCI Configuration Space ( XXX huh? )
*/
/*
* clocks are locked, read-only:
* Tx frequency & symbol clocks are derived from the same OSC
*/
/*
* Descriptor Polling State: enable test mode.
*/
/*
* undocumented bits which appear to control the power state of the RF
* components
*/
#define RTW_ANAPARM_RFPOW_MASK \
/*
* 1: disable Tx DAC,
* 0: enable
*/
/*
* undocumented bits which appear to control the power state of the RF
* components
*/
/*
*/
/*
* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
*/
/*
* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
*/
/*
*/
/*
* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
*/
/*
* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
*/
/*
*/
#define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \
#define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \
/*
* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
*/
#define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\
/*
* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
*/
#define RTW_ANAPARM_RFPOW_PHILIPS_OFF\
/*
* undocumented card-specific bits from the EEPROM.
*/
/*
* Network Type and Link Status
*/
/*
* AP, XXX RTL8181 only?
*/
/*
* infrastructure link ok
*/
/*
* ad-hoc link ok
*/
/*
* no link
*/
/*
* Set RTW_CONFIG3_PARMEN and RTW_9346CR_EEM_CONFIG to
* allow RTW_ANAPARM writes.
*/
/*
* Valid when RTW_CONFIG1_PMEN is set. If set, RTL8180 wakes up
* OS when Magic Packet is Rx'd.
*/
/*
* Cardbus-related registers and functions are enabled,
* read-only. XXX RTL8180 only.
*/
/*
* CLKRUN enabled, read-only. XXX RTL8180 only.
*/
/*
* Function Registers Enabled, read-only. XXX RTL8180 only.
*/
/*
* Fast back-to-back enabled, read-only.
*/
/*
* VCO Power Down
* 0: normal operation
* (power-on default)
* 1: power-down VCO, RF front-end,
* and most RTL8180 components.
*/
/*
* Power Off
* 0: normal operation
* (power-on default)
* 1: power-down RF front-end,
* and most RTL8180 components,
* but leave VCO on.
*
* XXX RFMD front-end only?
*/
/*
* Power Management
* 0: normal operation
* (power-on default)
* 1: set Tx packet's PWRMGMT bit.
*/
/*
* LANWAKE vs. PMEB: Cardbus-only
* 0: LWAKE & PMEB asserted
* simultaneously
* 1: LWAKE asserted only if
* both PMEB is asserted and
* ISOLATEB is low.
* XXX RTL8180 only.
*/
/*
* see RTW_CONFIG1_LWACT XXX RTL8180 only.
*/
/*
* Radio Front-End Programming Method
*/
/*
*/
/*
*/
/*
* Enable Tx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor
* RTW_CONFIG0_WEP104 is set.
*/
/*
* Enable Rx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor
* RTW_CONFIG0_WEP104 is set.
*/
/*
* TU between TBTT, written by host.
*/
/*
* ATIM Window length in TU, written by host.
*/
/*
* RTL8180 wakes host with RTW_INTR_BCNINT at BINTRITV
* microseconds before TBTT
*/
/*
* RTL8180 wakes host with RTW_INTR_ATIMINT at ATIMTRITV
* microseconds before end of ATIM Window
*/
/*
* Rev. C magic from reference driver
*/
/*
* microsecond Tx delay between MAC and RF front-end
*/
/*
* used for writing RTL8180's integrated baseband processor
*/
/*
* if !RTW_PHYCFG_HST, host sets. MAC clears after banging bits.
*/
/*
* 1: host bangs bits
* 0: MAC bangs bits
*/
/*
* 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1.
*/
/*
* 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0.
*/
/*
* Default Key Registers, each 128b
*
* If RTW_SCR_KM_WEP104, 104 lsb are the key.
* If RTW_SCR_KM_WEP40, 40 lsb are the key.
*/
/*
* 1: start calibration cycle and raise AGCRESET pin.
* 0: lower AGCRESET pin
*/
/*
* Enable LAN Wake signal, from EEPROM
*/
/*
* 1: both software & PCI Reset reset PME_Status
* 0: only software resets PME_Status
*
* From EEPROM.
*/
/*
* Transmit Priority Polling Register, 8b, write-only.
*/
/*
* RTL8180 clears to notify host of a beacon
* Tx. Host writes have no effect.
*/
/*
* Host writes 1 to notify RTL8180 of high-priority Tx packets, RTL8180 clears
* to after high-priority Tx is complete.
*/
/*
* If RTW_CONFIG2_DPS is set, host writes 1 to notify RTL8180 of
* normal-priority Tx packets, RTL8180 clears
* after normal-priority Tx is complete.
*
* If RTW_CONFIG2_DPS is clear, host writes have no effect. RTL8180 clears after
* normal-priority Tx is complete.
*/
/*
* Host writes 1 to notify RTL8180 of low-priority Tx packets, RTL8180 clears
* after low-priority Tx is complete.
*/
/*
* Host writes 1 to tell RTL8180 to stop beacon DMA. This bit is invalid
* when RTW_CONFIG2_DPS is set.
*/
/*
* Host writes 1 to tell RTL8180 to stop high-priority DMA.
*/
/*
* Host writes 1 to tell RTL8180 to stop normal-priority DMA.
* This bit is invalid when RTW_CONFIG2_DPS is set.
*/
/*
* Host writes 1 to tell RTL8180 to stop low-priority DMA.
*/
/* Start all queues. */
/* Start queues solaris required. */
/* Stop all queues. */
/*
* Contention Window: indicates number of contention windows before Tx
*/
/*
* Retry Count Register, 16b, read-only
*/
/*
* Retry Count: indicates number of retries after Tx
*/
/*
* Receive descriptor Start Address Register,
* 32b, 256-byte alignment.
*/
/*
* Function Event Register, 32b, Cardbus only. Only valid when
* both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
*/
/*
* Function Event Mask Register, 32b, Cardbus only. Only valid when
* both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
*/
/*
* Function Present State Register, 32b, read-only, Cardbus only.
* Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
* are set.
*/
/*
* Function Force Event Register, 32b, write-only, Cardbus only.
* Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
* are set.
*/
/*
* Serial EEPROM offsets
*/
/*
*/
/*
* the first descriptor in each ring must be on a 256-byte boundary
*/
/*
* Tx descriptor
*/
struct rtw_txdesc {
};
/*
* add short PLCP preamble and header
*/
/*
* Tx packet size in bytes
*/
/*
* supplements _LENGTH in packets sent 5.5Mb/s or faster
*/
/*
* RTS Duration (microseconds)
*/
/*
* Rx descriptor
*/
struct rtw_rxdesc {
};
/*
* buffer overflow XXX means FIFO exhausted?
*/
/*
* Rx'd with short preamble and PLCP header
*/
/*
* error summary. valid when RTW_RXSTAT_LS set. indicates
* that either RTW_RXSTAT_CRC32 or RTW_RXSTAT_ICV is set.
*/
/*
* XXX CRC16 error, from reference driver
*/
/*
* frame length, including CRC32
*/
/*
* Convenient status conjunction.
*/
/*
* Convenient status disjunctions.
*/
/*
* for Philips RF front-ends
*/
/*
* for RF front-ends by Intersil, Maxim, RFMD
*/
/*
* bus_space(9) lied?
*/
#ifndef BUS_SPACE_BARRIER_SYNC
#endif
#endif
#endif
#endif
#endif
/*
* Bus barrier
*
* ([reg1, reg0]) before starting new ops on the same region. See
* acceptable bus_space_barrier(9) for the flag definitions.
*/
/*
* ***just define a dummy macro here in solaris***
* bus_space_barrier((regs)->r_bh, (regs)->r_bt, \
* MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags)
*/
/*
* Barrier convenience macros.
*/
/*
* sync
*/
/*
* write-before-write
*/
/*
* write-before-read
*/
/*
* read-before-read
*/
/*
* read-before-read
*/
/*
* Registers for RTL8180L's built-in baseband modem.
*/
/*
* guess: low-noise amplifier activation threshold
*/
/*
* guess: intermediate frequency (IF)
* auto-gain control (AGC) initial value
*/
/*
* guess: activation threshold for IF AGC loop
*/
/*
*/
/*
* loopback rate?
* 0: 1Mbps
* 1: 2Mbps
* 2: 5.5Mbps
* 3: 11Mbps
*/
/*
* carrier-sense threshold
*/
/*
* guess: channel energy-detect threshold
*/
/*
* guess: channel signal-quality threshold
*/
#define RTW_EPROM_CMD_NORMAL 0
#ifdef __cplusplus
}
#endif
#endif /* _RTW_REG_H_ */