rtls.h revision bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2eb
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * CDDL HEADER START
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * The contents of this file are subject to the terms of the
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Common Development and Distribution License (the "License").
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * You may not use this file except in compliance with the License.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * or http://www.opensolaris.org/os/licensing.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * See the License for the specific language governing permissions
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * and limitations under the License.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * When distributing Covered Code, include this CDDL HEADER in each
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * If applicable, add the following below this CDDL HEADER, with the
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * fields enclosed by brackets "[]" replaced with your own identifying
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * information: Portions Copyright [yyyy] [name of copyright owner]
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * CDDL HEADER END
b420f3adeb349714478d1a7813d2c0e069d41555Richard Lowe * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Use is subject to license terms.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * This product is covered by one or more of the following patents:
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * US6,327,625.
19b94df933188a15d4f0d6c568f0bab3f127892eMatthew Ahrens * Currently supports:
19b94df933188a15d4f0d6c568f0bab3f127892eMatthew Ahrens/* Debug flags */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Driver support device
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_SUPPORT_DEVICE_1 ((RT_VENDOR_ID << 16) | RT_DEVICE_8139)
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* bind vendor and device id together */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_SUPPORT_DEVICE_2 ((RTLS_VENDOR_ID_2 << 16) | RTLS_DEVICE_ID_2)
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_SUPPORT_DEVICE_3 ((RTLS_VENDOR_ID_3 << 16) | RTLS_DEVICE_ID_3)
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_SUPPORT_DEVICE_4 ((RTLS_VENDOR_ID_4 << 16) | RTLS_DEVICE_ID_4)
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Driver tx/rx parameters
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_RX_BUF_SIZE (RTLS_RX_BUF_RING + 2*1024)
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_MCAST_BUF_SIZE 64 /* multicast hash table size in bits */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * RTL8139 CRC poly
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_HASH_POLY 0x04C11DB7 /* 0x04C11DB6 */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * STREAMS parameters
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_HIWAT (RTLS_MAX_TX_DESC * ETHERMAX)
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* driver flow control high water */
b420f3adeb349714478d1a7813d2c0e069d41555Richard Lowe#define RTLS_LOWAT 1 /* driver flow control low water */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Helpful defines for register access
b420f3adeb349714478d1a7813d2c0e069d41555Richard Lowe#define REG32(reg, off) ((uint32_t *)((uintptr_t)(reg) + off))
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define REG16(reg, off) ((uint16_t *)((uintptr_t)(reg) + off))
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define REG8(reg, off) ((uint8_t *)((uintptr_t)(reg) + off))
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrenstypedef struct {
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens ddi_acc_handle_t acc_hdl; /* handle for memory */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens ddi_dma_cookie_t cookie; /* associated cookie */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrenstypedef struct rtls_stats {
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens uint32_t no_carrier; /* dot3StatsCarrierSenseErrors */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens uint32_t xmt_latecoll; /* dot3StatsLateCollisions */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens uint32_t defer; /* dot3StatsDeferredTransmissions */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens uint32_t frame_err; /* dot3StatsAlignErrors */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrenstypedef struct rtls_instance {
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* instance name: "rtls" + instance num, 32 bytes is enough */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens caddr_t io_reg; /* mapped chip register address */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* io handle & iblock */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens ddi_acc_handle_t io_handle; /* ddi I/O handle */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* dma buffer alloc used */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens dma_area_t dma_area_rx; /* receive dma area */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* transmit dma area */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* used for multicast set */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* used for send */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens uint16_t tx_current_desc; /* Current Tx page */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* used for recv */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* send reschedule used */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* current MAC state */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* rtls statistics */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_TX_WAIT_TIMEOUT (void) (drv_usectohz(100 * 1000)) /* 100ms */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_RESET_WAIT_INTERVAL (void) (drv_usecwait(100))
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_RX_ADDR_ALIGNED(addr) (((addr + 3) & ~3) % RTLS_RX_BUF_RING)
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* 4-bytes aligned, also with RTLS_RX_BUF_RING boundary */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens/* parameter definition in rtls.conf file */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define FORCE_AUTO_NEGO 5 /* auto negotioation mode */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define FORCE_100_FDX 4 /* 100 full_duplex mode */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define FORCE_100_HDX 3 /* 100 half_duplex mode */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define FORCE_10_FDX 2 /* 10 full_duplex mode */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define FORCE_10_HDX 1 /* 10 half_duplex mode */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * RealTek 8129/8139 register offsets definition
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * MAC address register, initial value isautoloaded from the
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * EEPROM EthernetID field
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Multicast register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Transmit status register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_CS_LOST 0x80000000 /* Carrier Sense Lost */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_TX_ABORT 0x40000000 /* Transmit Abort */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_OWC 0x20000000 /* Out of Window Collision */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_CDH 0x10000000 /* CD Heart Beat */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_NCC 0x0f000000 /* Number of Collision Count */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_TX_THRESHOLD 0x003f0000 /* Early Tx Threshold */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_TX_THRESHOLD_MAX 0x3f /* 0x3f * 32 Bytes */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_TX_OK 0x00008000 /* Transmit OK */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_TX_UNDERRUN 0x00004000 /* Transmit FIFO Underrun */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_STATUS_OWN 0x00002000 /* RTL8139 Own bit */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* The total size in bytes of the data in this descriptor */
b420f3adeb349714478d1a7813d2c0e069d41555Richard Lowe * The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * by the RTL8139 when the Transmit Byte Count (bit12-0) in the corresponding
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Tx descriptor is written. If h/w transmit finish, at least some of these
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * bits are none zero.
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_COMPLETE_FLAG (TX_STATUS_TX_ABORT | TX_STATUS_TX_OK | \
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_ERR_FLAG (TX_STATUS_TX_ABORT | TX_STATUS_TX_UNDERRUN | \
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Transmit start address of descriptors
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Receive buffer start address
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Early receive byte count register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Commond register
b420f3adeb349714478d1a7813d2c0e069d41555Richard Lowe * Rx current read address register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Value in RX_CURRENT_READ_ADDR_REG is 16 less than
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * the actual rx read address
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Interrupt register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RTLS_RX_INT (RX_OK_INT | RX_ERR_INT | \
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RX_OVERFLOW_INT (RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT)
19b94df933188a15d4f0d6c568f0bab3f127892eMatthew Ahrens#define RTLS_INT_MASK (LINK_CHANGE_INT | TX_ERR_INT | TX_OK_INT | \
19b94df933188a15d4f0d6c568f0bab3f127892eMatthew Ahrens RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT | \
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Transmit configuration register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens /* re-transmit count (16 + 1 * 16) = 32 times before aborting */
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Receive configuration register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RX_ACCEPT_BROADCAST_PACKET 0x000000008
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RX_ACCEPT_MULTICAST_PACKET 0x000000004
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RX_ACCEPT_MAC_MATCH_PACKET 0x000000002
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens#define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \
b420f3adeb349714478d1a7813d2c0e069d41555Richard Lowe * Missed packet counter: indicates the number of packets
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * discarded due to rx FIFO overflow
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * 93c46(93c56) commond register:
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Configuration registers
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Media status register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Multiple interrupt select register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Transmit status of all descriptor registers register
cde58dbc6a23d4d38db7c8866312be83221c765fMatthew Ahrens * Basic mode control register
#ifdef __cplusplus