/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _RGE_HW_H
#define _RGE_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* First section:
* Identification of the various Realtek GigE chips
*/
/*
* Driver support device
*/
/*
* Second section:
* Offsets of important registers & definitions for bits therein
*/
/*
* MAC address register, initial value is autoloaded from the
* EEPROM EthernetID field
*/
/*
* Multicast register
*/
/*
* Dump Tally Counter Command register
*/
/*
* Register for start address of transmit descriptors
*/
/*
* Commond register
*/
/*
* Transmit priority polling register
*/
/*
* Interrupt mask & status register
*/
RGE_RX_INT | LINK_CHANGE_INT | \
/*
* Transmit configuration register
*/
/*
* Receive configuration register
*/
/*
* Timer count register
*/
/*
* Missed packet counter: indicates the number of packets
* discarded due to Rx FIFO overflow
*/
/*
* 93c46(93c56) commond register:
*/
/*
* Configuration registers
*/
/*
* Config 5 Register Bits
*/
/*
* Timer interrupt register
*/
/*
* PHY access register
*/
/*
* CSI data register (for PCIE chipset)
*/
/*
* CSI access register (for PCIE chipset)
*/
/*
* PHY status register
*/
#define RGE_SPEED_UNKNOWN 0
/*
* EPHY access register (for PCIE chipset)
*/
/*
* Receive packet maximum size register
* -- the maximum rx size supported is (16K - 1) bytes
*/
/*
* C+ command register
*/
/*
* Receive descriptor start address
*/
/*
* Max transmit packet size register
*/
/*
* PHY registers
*/
/*
* Basic mode control register
*/
/*
* Basic mode status register
*/
/*
* PHY identifier register
*/
/*
* Auto-negotiation advertising register
*/
/*
* Auto-negotiation link partner ability register
*/
/*
* Auto-negotiation expansion register
*/
/*
* Auto-negotiation next page transmit register
*/
/*
* Auto-negotiation next page receive register
*/
/*
* 1000Base-T control register
*/
/*
* 1000Base-T status register
*/
/*
* 1000Base-T extended status register
*/
/*
*/
/*
* Bits in the MII_1000BASE_T_CONTROL register
*
* (otherwise, roles are automatically negotiated). When this bit is set,
* the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced.
*/
/*
* Vendor-specific MII registers
*/
/*
* Bits in the MII_AUX_STATUS register
*/
/*
* Third section:
* Hardware-defined data structures
*
* Note that the chip is naturally little-endian, so, for a little-endian
* host, the structures defined below match those descibed in the PRM.
* For big-endian hosts, some structures have to be swapped around.
*/
#if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN)
#endif
/*
* Architectural constants: absolute maximum numbers of each type of ring
*/
typedef struct rge_bd {
} rge_bd_t;
/*
* Chip VLAN TCI format
* bit0-3: VIDH The high 4 bits of a 12-bit VLAN ID
* bit4: CFI Canonical format indicator
* bit5-7: 3-bit 8-level priority
* bit8-15: The low 8 bits of a 12-bit VLAN ID
*/
/*
* Hardware-defined Status Block
*/
typedef struct rge_hw_stats {
#ifdef __cplusplus
}
#endif
#endif /* _RGE_HW_H */