/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 NetXen, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include <sys/ethernet.h>
#include <sys/dditypes.h>
#include <sys/sysmacros.h>
#include "unm_nic.h"
#include "unm_nic_hw.h"
#include "nic_cmn.h"
#include "unm_nic_ioctl.h"
#include "nic_phan_reg.h"
struct crb_addr_pair {
};
static void
crb_addr_transform_setup(void)
{
/*
* Used only in P3 just define it for P2 also.
*/
}
/*
* decode_crb_addr(0 - utility to translate from internal Phantom CRB address
* to external PCI CRB address.
*/
static unsigned long
{
int i;
for (i = 0; i < MAX_CRB_XFORM; i++) {
if (crb_addr_xform[i] == base_addr) {
pci_base = i << 20;
break;
}
}
if (pci_base == ADDR_ERROR) {
return (pci_base);
} else {
}
}
static int
{
long timeout = 0;
while (!done) {
/* acquire semaphore2 from PCI HW block */
if (done == 1)
break;
if (timeout >= rom_lock_timeout) {
return (-1);
}
timeout++;
}
return (0);
}
static void
{
/* release semaphore2 */
}
static int
{
long timeout = 0;
long done = 0;
while (done == 0) {
done &= 2;
timeout++;
if (timeout >= rom_max_timeout) {
"Timeout reached waiting for rom done");
return (-1);
}
}
return (0);
}
static int
{
return (-1);
}
// reset abyte_cnt and dummy_byte_cnt
return (0);
}
int
{
int ret;
return (-1);
}
if (ret != 0) {
return (-1);
}
return (ret);
}
int
{
unsigned long off;
unsigned int offset;
if (status)
if (verbose) {
int val;
else
else
else
}
if (rom_fast_read(adapter, 0, &n) != 0 ||
(unsigned int)n != 0xcafecafe ||
"n: %08x\n", unm_nic_driver_name, n);
return (-1);
}
offset = n & 0xffffU;
n = (n >> 16) & 0xffffU;
} else {
if (rom_fast_read(adapter, 0, &n) != 0 ||
!(n & 0x80000000)) {
"n: %08x\n", unm_nic_driver_name, n);
return (-1);
}
offset = 1;
n &= ~0x80000000;
}
if (n >= 1024) {
return (-1);
}
if (verbose)
unm_nic_driver_name, n);
return (-1);
}
for (i = 0; i < n; i++) {
return (-1);
}
if (verbose)
(unsigned int)decode_crb_addr(
}
for (i = 0; i < n; i++) {
/* skipping cold reboot MAGIC */
continue;
}
/* do not reset PCI */
continue;
}
continue;
continue;
continue;
}
/* skip the function enable register */
continue;
}
continue;
}
continue;
}
}
if (off == ADDR_ERROR) {
continue;
}
/* After writing this register, HW needs time for CRB */
/* to quiet down (else crb_window returns 0xffffffff) */
if (off == UNM_ROMUSB_GLB_SW_RESET) {
init_delay = 1;
/* hold xdma in reset also */
}
}
if (init_delay == 1) {
init_delay = 0;
}
}
// disable_peg_cache_all
// unreset_net_cache
adapter);
}
// p2dn replyCount
// disable_peg_cache 0
// disable_peg_cache 1
// peg_clr_all
// peg_clr 0
// peg_clr 1
// peg_clr 2
// peg_clr 3
return (0);
}
int
{
if (!pegtune_val) {
do {
if ((val == PHAN_INITIALIZE_COMPLETE) ||
(val == PHAN_INITIALIZE_ACK))
return (DDI_SUCCESS);
/* 500 msec wait */
drv_usecwait(500000);
} while (--retries > 0);
if (!retries) {
"failed...state:%d\n", val);
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
int
{
int i;
data = 1;
&data, 4);
}
for (i = 0; i < size; i++) {
"Will skip loading flash image\n");
return (DDI_FAILURE);
}
flashaddr += 4;
memaddr += 4;
}
drv_usecwait(100);
data = 0x80001d;
&data, 4);
} else {
data = 0x3fff;
data = 0;
&data, 4);
}
return (DDI_SUCCESS);
}