/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 NetXen, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _UNM_INC_H_
#define _UNM_INC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "nx_errorcode.h"
#define PREALIGN(x)
#define POSTALIGN(x)
typedef char __int8_t;
typedef short __int16_t;
typedef int __int32_t;
typedef long long __int64_t;
typedef unsigned char __uint8_t;
typedef unsigned short __uint16_t;
typedef unsigned int __uint32_t;
typedef unsigned long long __uint64_t;
typedef unsigned long long u64;
typedef unsigned long long U64;
#include "nx_hw_pci_regs.h"
/*
* MAX_RCV_CTX : The number of receive contexts that are available on
* the phantom.
*/
/* ------------------------------------------------------------------------ */
/* CRB Hub and Agent addressing */
/* ------------------------------------------------------------------------ */
/*
* WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an
* ILLEGAL hub!!!!!
*/
/*
* WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an
* ILLEGAL hub!!!!!
*/
/* Hub 0 */
/* Hub 1 */
/* Hub 2 */
/* Hub 3 */
/* Hub 4 */
/* Hub 5 */
/* Hub 6 */
/* This field defines PCI/X adr [25:20] of agents on the CRB */
/* */
#define UNM_HW_PX_MAP_CRB_PH 0
/* N/A: Not use in either Phantom1 or Phantom2 => use for TIMR */
/* #define PX_MAP_CRB_C2C2 40 */
/* #define PX_MAP_CRB_SS 41 */
/* This field defines CRB adr [31:20] of the agents */
/* */
/*
* ROM USB CRB space is divided into 4 regions depending on decode of
* address bits [19:16]
*/
/* ROMUSB GLB register definitions */
/* Lock IDs for ROM lock */
/* Lock IDs for PHY lock */
/* HACK upon HACK upon HACK (for PCIE builds) */
// window 1 pcie slot
/*
* ====================== BASE ADDRESSES ON-CHIP ======================
* Base addresses of major components on-chip.
* ====================== BASE ADDRESSES ON-CHIP ======================
*/
/*
* Imbus address bit used to indicate a host address. This bit is
* eliminated by the pcie bar and bar select before presentation
* over pcie.
*/
/* host memory via IMBUS */
/*
* The ifdef at the bottom should go. All drivers should start using the
* above 2 defines.
*/
#ifdef P3
#else
#endif
/* we're mapping 128MB of mem on the PCI bus */
/*
*/
/*
* h/w block.
*/
/*
* Configuration registers.
*/
/* P3 802.3ap */
/*
* Register offsets for MN
*/
/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
/* XG Link status */
/* ====================== Configuration Constants ======================== */
/* ============================= 1GbE =============================== */
/* Nibble or Byte mode for phy interface (GbE mode only) */
typedef enum {
UNM_NIU_10_100_MB = 0,
/* Promiscous mode options (GbE mode only) */
typedef enum {
/*
* NIU GB Drop CRC Register
*/
typedef struct {
/*
* NIU GB GMII Mode Register (applies to GB0, GB1, GB2, GB3)
* To change the mode, turn off the existing mode, then turn on the new mode.
*/
typedef struct {
/*
* NIU GB MII Mode Register (applies to GB0, GB1, GB2, GB3)
* To change the mode, turn off the existing mode, then turn on the new mode.
*/
typedef struct {
/*
* NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
/*
* NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
/*
* NIU XG Pause Ctl Register
*/
typedef struct {
/*
* NIU GBe Pause Ctl Register
*/
typedef struct {
/*
* NIU XG MAC Config Register
*/
typedef struct {
/*
* NIU GB MII Mgmt Config Register (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
/* 4:clk/10, 5:clk/14, 6:clk/20, 7:clk/28 */
/*
* NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
/*
* NIU GB MII Mgmt Address Register (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
/*
* NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
* Read-only register.
*/
typedef struct {
/*
* NIU GB Station Address High Register
* NOTE: this value is in network byte order.
*/
typedef struct {
/*
* NIU GB Station Address Low Register
* NOTE: this value is in network byte order.
*/
typedef struct {
/* ============================ PHY Definitions ========================== */
/*
*/
typedef enum {
/*
* PHY-Specific Status Register (reg 17).
*/
typedef struct {
/* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m */
/*
* Interrupt Register definition
* This definition applies to registers 18 and 19 (int enable and int status).
*/
typedef struct {
/* ============================= 10GbE =============================== */
/*
* NIU Mode Register.
*/
typedef struct {
/* ========================== Interface Functions ======================= */
/* Generic enable for GbE ports. Will detect the speed of the link. */
long unm_niu_gbe_init_port(long port);
/* XG Link status */
#define XG_LINK_UNKNOWN_P3 0
/*
*/
typedef union {
struct {
/*
* =1 if watchdog is active.
* =0 if watchdog is inactive
* This is read-only for anyone
* but the watchdog itself.
*/
/*
* Set this to 1 to send disable
* request to watchdog . Watchdog
* will complete the shutdown
* process and acknowledge it
* by clearing this bit and the
* "enable" bit.
*/
/*
* Set this to 1 to send enable
* request to watchdog . Watchdog
* will complete the enable
* process and acknowledge it
* by clearing this bit and
* setting the "enable" bit.
*/
} s1;
#define UNM_PORT_MODE_NONE 0
/*
* Following define address space withing PCIX CRB space to talk with
* devices on the storage side PCI bus.
*/
/*
* Configuration registers. These are the same offsets on both host and
* storage side PCI blocks.
*/
/* Used for PS PCI Memory access */
/*
* CRB window register.
*/
typedef struct {
/*
* Tell which interrupt source we want to operate on.
*/
typedef enum {
typedef enum {
/*
* PCIX Interrupt Mask Register.
*/
typedef struct {
/* 0=DMA0 not masked, 1=masked */
/* 0=DMA1 not masked, 1=masked */
/* 0=I2Q not masked, 1=masked */
// These are offset to a particular Peg's CRB base address
/*
* to either the Primary Queue Manager or the Secondary Queue Manager.
*/
/*
* General configuration constants.
*/
/*
* Data movement registers (differs based on processor).
*/
(W)*sizeof (unm_dataword_t))
(W)*sizeof (unm_dataword_t))
/*
* Control commands to the QM block.
*/
/*
* Platform-specific fields in the queue command word
*/
#define UNM_QM_CMD_SIDE 0
/* Casper and Peg need this bit. PCI interface does not */
/*
* Pegasus has two QM ports. This is the default one to use (unless
* QM async interface is called explicitly with other port).
*/
#define UNM_QM_DEFAULT_PORT 0
/*
* Status result returned to caller of unm_qm_request_status()
*/
typedef enum {
/* error in HW - most likely PCI bug. retry */
/*
*/
/*
* Configuration registers.
*/
/*
* List the bit positions in the registers of the interrupt sources.
*/
typedef enum {
/* [29:31] reserved */
/* [48:63] reserved */
/*
*/
typedef struct {
typedef struct {
/*
* List the possible interrupt sources and the
* control operations to be performed for each.
*/
typedef enum {
typedef enum {
/*
* h/w block.
*/
/*
* Configuration registers.
*/
#define UNM_SQM_BASE(G) \
((G) == 0 ? UNM_CRB_SQM_NET_0 : \
((G) == 1 ? UNM_CRB_SQM_NET_1 : \
/*
* Interrupt enables and interrupt status for all 16 queues in a group.
*/
typedef struct {
/*
* Control operation for an SQM Group interrupt.
*/
typedef enum {
typedef enum {
unsigned long unm_xport_lock(void);
void unm_xport_unlock(unsigned long);
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
do { \
} while (0)
do { \
} while (0)
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
/*
* Configuration registers.
*/
#ifdef PCIX
#else
#endif
// FOR PORT 1
// FOR PORT 2
// PORT 3
/*
* The PCI VendorID and DeviceID for our board.
*/
/*
* Time base tick control registers (global and per-flow).
*/
typedef struct {
/* half period of time cycle */
/* global: in units of core clock */
/* per-flow: in units of global ticks */
typedef struct
{
typedef struct {
#define UNM_MIU_TEST_AGENT_CMD_READ 0
#ifdef __cplusplus
}
#endif
#endif /* _UNM_INC_H_ */