nge_chip.h revision 47693af92e50a1ad81825eb01b7157a211269613
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NGE_CHIP_H
#define _SYS_NGE_CHIP_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include "nge.h"
#define VENDOR_ID_NVIDIA 0x10de
#define DEVICE_ID_MCP04_37 0x37
#define DEVICE_ID_MCP04_38 0x38
#define DEVICE_ID_CK804_56 0x56
#define DEVICE_ID_CK804_57 0x57
#define DEVICE_ID_MCP51_269 0x269
#define DEVICE_ID_MCP51_268 0x268
#define DEVICE_ID_MCP55_373 0x373
#define DEVICE_ID_MCP55_372 0x372
#define DEVICE_ID_MCP61_3EE 0x3ee
#define DEVICE_ID_MCP61_3EF 0x3ef
#define DEVICE_ID_NF3_E6 0xe6
#define DEVICE_ID_NF3_DF 0xdf
#define PCI_CONF_HT_INTERNAL 0x4c
typedef union _nge_interbus_conf {
struct {
} conf_bits;
/* Private PCI configuration register for MSI mask of mcp55 */
#define PCI_CONF_HT_MSI_MASK 0x60
typedef union _nge_msi_mask_conf {
struct {
/* Private PCI configuration register for MSI map capability of mcp55 */
#define PCI_CONF_HT_MSI_MAP_CAP 0x6c
typedef union _nge_msi_map_cap_conf {
struct {
/*
* Master interrupt
*/
#define NGE_INTR_SRC 0x000
#define INTR_SRC_ALL 0x00007fff
typedef union _nge_intr_src {
struct {
} int_bits;
} nge_intr_src;
/*
* Master interrupt Mask
*/
#define NGE_INTR_MASK 0x004
#define NGE_INTR_ALL_EN 0x00007fff
typedef union _nge_intr_mask {
struct {
} mask_bits;
/*
* Software timer control register
*/
#define NGE_SWTR_CNTL 0x008
typedef union _nge_swtr_cntl {
struct {
} cntl_bits;
/*
* Software Timer Interval
*/
#define NGE_SWTR_ITC 0x00c
#define POLL_LWATER 0x10
#define INTR_HWATER 0x5
#define SWTR_ITC 0x10
typedef union _nge_itc {
struct {
} itc_bits;
} nge_itc;
/*
* Fatal error register
*/
#define NGE_REG010 0x010
typedef union _nge_reg010 {
struct {
} reg010_bits;
} nge_reg010;
/*
* MSI vector map register 0
*/
#define NGE_MSI_MAP0 0x020
typedef union _nge_msi_map0_vec {
struct {
} vecs_bits;
/*
* MSI vector map register 1
*/
#define NGE_MSI_MAP1 0x024
typedef union _nge_msi_map1_vec {
struct {
} vecs_bits;
/*
* MSI vector map register 2
*/
#define NGE_MSI_MAP2 0x028
/*
* MSI vector map register 2
*/
#define NGE_MSI_MAP3 0x02c
/*
* MSI mask register for mcp55
*/
#define NGE_MSI_MASK 0x30
typedef union _nge_msi_mask {
struct {
/*
* Software misc register for mcp51
*/
#define NGE_SOFT_MISC 0x034
typedef union _nge_soft_misc {
struct {
} misc_bits;
/*
* DMA configuration
*/
#define NGE_DMA_CFG 0x040
typedef union _nge_dma_cfg {
struct {
} cfg_bits;
} nge_dma_cfg;
/*
* Request DMA configuration
*/
#define NGE_DMA_RCFG 0x044
typedef union _nge_dma_rcfg {
struct {
} rcfg_bis;
} nge_dma_rcfg;
/*
* Hot DMA configuration
*/
#define NGE_DMA_HOT_CFG 0x048
typedef union _nge_dma_hcfg {
struct {
} hcfg_bits;
} nge_dma_hcfg;
/*
* PMU control register 0 for mcp51
*/
#define NGE_PMU_CNTL0 0x060
#define NGE_PMU_CORE_SPD10_BUSY 0x8
#define NGE_PMU_CORE_SPD10_IDLE 0xB
#define NGE_PMU_CORE_SPD100_BUSY 0x4
#define NGE_PMU_CORE_SPD100_IDLE 0x7
#define NGE_PMU_CORE_SPD1000_BUSY 0x0
#define NGE_PMU_CORE_SPD1000_IDLE 0x3
typedef union _nge_pmu_cntl0 {
struct {
} cntl0_bits;
/*
* PMU control register 1 for mcp51
*/
#define NGE_PMU_CNTL1 0x064
typedef union _nge_pmu_cntl1 {
struct {
} cntl1_bits;
/*
* PMU control register 2 for mcp51
*/
#define NGE_PMU_CNTL2 0x068
typedef union _nge_pmu_cntl2 {
struct {
} cntl2_bits;
/*
* PMU core idle limit register for mcp51
*/
#define NGE_PMU_CIDLE_LIMIT 0x06c
#define NGE_PMU_CIDLE_LIMIT_DEF 0xffff
/*
* PMU device idle limit register for mcp51
*/
#define NGE_PMU_DIDLE_LIMIT 0x070
#define NGE_PMU_DIDLE_LIMIT_DEF 0xffff
/*
* PMU core idle count value register for mcp51
*/
#define NGE_PMU_CIDLE_COUNT 0x074
#define NGE_PMU_CIDEL_COUNT_DEF 0xffff
/*
* PMU device idle count value register for mcp51
*/
#define NGE_PMU_DIDLE_COUNT 0x078
#define NGE_PMU_DIDEL_COUNT_DEF 0xffff
/*
* Transmit control
*/
#define NGE_TX_CNTL 0x080
typedef union _nge_tx_cntl {
struct {
} cntl_bits;
} nge_tx_cntl;
/*
* Transmit enable
* Note: for ck804 or mcp51, this is 8-bit register;
* for mcp55, it is a 32-bit register.
*/
#define NGE_TX_EN 0x084
typedef union _nge_tx_en {
struct {
} bits;
} nge_tx_en;
/*
* Transmit status
*/
#define NGE_TX_STA 0x088
typedef union _nge_tx_sta {
struct {
} sta_bits;
} nge_tx_sta;
/*
* Receive control
*/
#define NGE_RX_CNTL0 0x08c
typedef union _nge_rx_cntrl0 {
struct {
} cntl_bits;
/*
* Maximum receive Frame size
*/
#define NGE_RX_CNTL1 0x090
typedef union _nge_rx_cntl1 {
struct {
} cntl_bits;
} nge_rx_cntl1;
/*
* Receive enable register
* Note: for ck804 and mcp51, this is a 8-bit register;
* for mcp55, it is a 32-bit register.
*/
#define NGE_RX_EN 0x094
typedef union _nge_rx_en {
struct {
} bits;
} nge_rx_en;
/*
* Receive status register
*/
#define NGE_RX_STA 0x098
typedef union _nge_rx_sta {
struct {
} sta_bits;
} nge_rx_sta;
/*
* Backoff Control
*/
#define NGE_BKOFF_CNTL 0x09c
#define BKOFF_RSEED 0x8
#define BKOFF_SLIM_GMII 0x3ff
#define BKOFF_SLIM_MII 0x7f
typedef union _nge_bkoff_cntl {
struct {
} bkoff_bits;
/*
* Transmit defferral timing
*/
#define NGE_TX_DEF 0x0a0
#define TX_TIFG_MII 0x15
#define TX_IFG_RGMII_1000_FD 0x14
#define TX_IFG_RGMII_OTHER 0x16
#define TX_IFG2_MII 0x5
#define TX_IFG2_RGMII_10_100 0x7
#define TX_IFG2_RGMII_1000 0x5
#define TX_IFG2_DEFAULT 0X0
#define TX_IFG1_DEFAULT 0xf
typedef union _nge_tx_def {
struct {
} def_bits;
} nge_tx_def;
/*
* Receive defferral timing
*/
#define NGE_RX_DEf 0x0a4
#define RX_DEF_DEFAULT 0x16
typedef union _nge_rx_def {
struct {
} def_bits;
} nge_rx_def;
/*
* Low 32 bit unicast address
*/
#define NGE_UNI_ADDR0 0x0a8
union {
struct {
} addr_bits;
/*
* High 32 bit unicast address
*/
#define NGE_UNI_ADDR1 0x0ac
typedef union _nge_uni_addr1 {
struct {
} addr_bits;
/*
* Low 32 bit multicast address
*/
#define NGE_MUL_ADDR0 0x0b0
union {
struct {
/*
* High 32 bit multicast address
*/
#define NGE_MUL_ADDR1 0x0b4
typedef union _nge_mul_addr1 {
struct {
/*
* Low 32 bit multicast mask
*/
#define NGE_MUL_MASK 0x0b8
union {
struct {
} mask_bits;
/*
* High 32 bit multicast mask
*/
#define NGE_MUL_MASK1 0x0bc
union {
struct {
} mask_bits;
/*
* Mac-to Phy Interface
*/
#define NGE_MAC2PHY 0x0c0
#define low_speed 0x0
#define fast_speed 0x1
#define giga_speed 0x2
#define err_speed 0x4
#define MII_IN 0x0
#define RGMII_IN 0x1
#define ERR_IN1 0x3
#define ERR_IN2 0x4
typedef union _nge_mac2phy {
struct {
} m2p_bits;
} nge_mac2phy;
/*
* Transmit Descriptor Ring address
*/
#define NGE_TX_DADR 0x100
typedef union _nge_tx_addr {
struct {
} addr_bits;
} nge_tx_addr;
/*
* Receive Descriptor Ring address
*/
#define NGE_RX_DADR 0x104
typedef union _nge_rx_addr {
struct {
} addr_bits;
} nge_rx_addr;
/*
*/
#define NGE_RXTX_DLEN 0x108
typedef union _nge_rxtx_dlen {
struct {
} dlen_bits;
/*
* Transmit polling register
*/
#define NGE_TX_POLL 0x10c
#define TX_POLL_INTV_1G 10
#define TX_POLL_INTV_100M 100
#define TX_POLL_INTV_10M 1000
typedef union _nge_tx_poll {
struct {
} poll_bits;
} nge_tx_poll;
/*
* Receive polling register
*/
#define NGE_RX_POLL 0x110
#define RX_POLL_INTV_1G 10
#define RX_POLL_INTV_100M 100
#define RX_POLL_INTV_10M 1000
typedef union _nge_rx_poll {
struct {
} poll_bits;
} nge_rx_poll;
/*
* Transmit polling count
*/
#define NGE_TX_PCNT 0x114
union {
struct {
} cnt_bits;
} nge_tx_pcnt;
/*
* Receive polling count
*/
#define NGE_RX_PCNT 0x118
union {
struct {
} cnt_bits;
} nge_rx_pcnt;
/*
* Current tx's descriptor address
*/
#define NGE_TX_CUR_DADR 0x11c
union {
struct {
} addr_bits;
/*
* Current rx's descriptor address
*/
#define NGE_RX_CUR_DADR 0x120
union {
struct {
} addr_bits;
/*
* Current tx's data buffer address
*/
#define NGE_TX_CUR_PRD0 0x124
union {
struct {
} prd0_bits;
/*
* Current tx's data buffer status
*/
#define NGE_TX_CUR_PRD1 0x128
union {
struct {
} prd1_bits;
/*
* Current rx's data buffer address
*/
#define NGE_RX_CUR_PRD0 0x12c
union {
struct {
/*
* Current rx's data buffer status
*/
#define NGE_RX_CUR_PRD1 0x130
/*
* Next tx's descriptor address
*/
#define NGE_TX_NXT_DADR 0x134
union {
struct {
/*
* Next rx's descriptor address
*/
#define NGE_RX_NXT_DADR 0x138
union {
struct {
} addr_bits;
/*
* Transmit fifo watermark
*/
#define NGE_TX_FIFO_WM 0x13c
#define TX_FIFO_TBFW 0
#define TX_FIFO_NOB_WM_MII 1
#define TX_FIFO_NOB_WM_GMII 8
#define TX_FIFO_DATA_LWM 0x20
#define TX_FIFO_PRD_LWM 0x8
#define TX_FIFO_PRD_HWM 0x38
typedef union _nge_tx_fifo_wm {
struct {
} wm_bits;
/*
* Receive fifo watermark
*/
#define NGE_RX_FIFO_WM 0x140
typedef union _nge_rx_fifo_wm {
struct {
} wm_bits;
/*
* Chip mode control
*/
#define NGE_MODE_CNTL 0x144
#define DESC_MCP1 0x0
#define DESC_OFFLOAD 0x1
#define DESC_HOT 0x2
#define DESC_RESV 0x3
#define MACHINE_BUSY 0x0
#define MACHINE_IDLE 0x1
typedef union _nge_mode_cntl {
struct {
} mode_bits;
#define NGE_TX_DADR_HI 0x148
#define NGE_RX_DADR_HI 0x14c
/*
* Mii interrupt register
* Note: for mcp55, this is a 32-bit register.
*/
#define NGE_MINTR_SRC 0x180
typedef union _nge_mintr_src {
struct {
} src_bits;
/*
* Mii interrupt mask
* Note: for mcp55, this is a 32-bit register.
*/
#define NGE_MINTR_MASK 0x184
typedef union _nge_mintr_mask {
struct {
} mask_bits;
/*
* Mii control and status
*/
#define NGE_MII_CS 0x188
#define MII_POLL_INTV 0x4
typedef union _nge_mii_cs {
struct {
} cs_bits;
} nge_mii_cs;
/*
* Mii Clock timer register
*/
#define NGE_MII_TM 0x18c
typedef union _nge_mii_tm {
struct {
} tm_bits;
} nge_mii_tm;
/*
* Mdio address
*/
#define NGE_MDIO_ADR 0x190
typedef union _nge_mdio_adr {
struct {
} adr_bits;
} nge_mdio_adr;
/*
* Mdio data
*/
#define NGE_MDIO_DATA 0x194
/*
* Power Management and Control
*/
#define NGE_PM_CNTL 0x200
typedef union _nge_pm_cntl {
struct {
/*
* mp_en: Magic Packet Enable
* pm_en: Pattern Match Enable
* lc_en: Link Change Enable
*/
} cntl_bits;
} nge_pm_cntl;
#define NGE_MPT_CRC0 0x204
#define NGE_PMC_MK00 0x208
#define NGE_PMC_MK01 0x20C
#define NGE_PMC_MK02 0x210
#define NGE_PMC_MK03 0x214
#define NGE_MPT_CRC1 0x218
#define NGE_PMC_MK10 0x21c
#define NGE_PMC_MK11 0x220
#define NGE_PMC_MK12 0x224
#define NGE_PMC_MK13 0x228
#define NGE_MPT_CRC2 0x22c
#define NGE_PMC_MK20 0x230
#define NGE_PMC_MK21 0x234
#define NGE_PMC_MK22 0x238
#define NGE_PMC_MK23 0x23c
#define NGE_MPT_CRC3 0x240
#define NGE_PMC_MK30 0x244
#define NGE_PMC_MK31 0x248
#define NGE_PMC_MK32 0x24c
#define NGE_PMC_MK33 0x250
#define NGE_MPT_CRC4 0x254
#define NGE_PMC_MK40 0x258
#define NGE_PMC_MK41 0x25c
#define NGE_PMC_MK42 0x260
#define NGE_PMC_MK43 0x264
#define NGE_PMC_ALIAS 0x268
#define NGE_PMCSR_ALIAS 0x26c
/*
* Seeprom control
*/
#define NGE_EP_CNTL 0x500
#define EEPROM_CLKDIV 249
#define EEPROM_WAITCLK 0x7
typedef union _nge_cp_cntl {
struct {
} cntl_bits;
} nge_cp_cntl;
/*
* Seeprom cmd control
*/
#define NGE_EP_CMD 0x504
#define SEEPROM_CMD_READ 0x0
#define SEEPROM_CMD_WRITE_ENABLE 0x1
#define SEEPROM_CMD_ERASE 0x2
#define SEEPROM_CMD_WRITE 0x3
#define SEEPROM_CMD_ERALSE_ALL 0x4
#define SEEPROM_CMD_WRITE_ALL 0x5
#define SEEPROM_CMD_WRITE_DIS 0x6
#define SEEPROM_READY 0x1
typedef union _nge_ep_cmd {
struct {
} cmd_bits;
} nge_ep_cmd;
/*
* Seeprom data register
*/
#define NGE_EP_DATA 0x508
typedef union _nge_ep_data {
struct {
} data_bits;
} nge_ep_data;
/*
* Power management control 2nd register (since MCP51)
*/
#define NGE_PM_CNTL2 0x600
typedef union _nge_pm_cntl2 {
struct {
} cntl_bits;
} nge_pm_cntl2;
/*
* ASF RAM 0x800-0xfff
*/
/*
* Hardware-defined Statistics Block Offsets
*
* These are given in the manual as addresses in NIC memory, starting
* from the NIC statistics area base address of 0x2000;
*/
#define KS_BASE 0x0280
typedef enum {
/*
* Hardware-defined Statistics Block
*
* Another view of the statistic block, as a array and a structure ...
*/
typedef union {
struct {
} s;
/*
*/
#define NGE_PHY_NUMBER 32
#define MII_LP_ASYM_PAUSE 0x0800
#define MII_LP_PAUSE 0x0400
#define MII_100BASE_T4 0x0200
#define MII_100BASET_FD 0x0100
#define MII_100BASET_HD 0x0080
#define MII_10BASET_FD 0x0040
#define MII_10BASET_HD 0x0020
#define MII_ID_MARVELL 0x5043
#define MII_ID_CICADA 0x03f1
#define MII_IDL_MASK 0xfc00
#define MII_AN_LPNXTPG 8
#define MII_IEEE_EXT_STATUS 15
/*
* New bits in the MII_CONTROL register
*/
#define MII_CONTROL_1000MB 0x0040
/*
* New bits in the MII_AN_ADVERT register
*/
#define MII_ABILITY_ASYM_PAUSE 0x0800
#define MII_ABILITY_PAUSE 0x0400
/*
* Values for the <selector> field of the MII_AN_ADVERT register
*/
#define MII_AN_SELECTOR_8023 0x0001
/*
* Bits in the MII_1000BASE_T_CONTROL register
*
* (otherwise, roles are automatically negotiated). When this bit is set,
* the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced.
*/
#define MII_1000BASE_T_CONTROL 9
#define MII_1000BT_CTL_ADV_FDX 0x0200
#define MII_1000BT_CTL_ADV_HDX 0x0100
/*
* Bits in the MII_1000BASE_T_STATUS register
*/
#define MII_1000BASE_T_STATUS 10
#define MII_1000BT_STAT_MASTER_FAULT 0x8000
#define MII_1000BT_STAT_MASTER_MODE 0x4000
#define MII_1000BT_STAT_LCL_RCV_OK 0x2000
#define MII_1000BT_STAT_RMT_RCV_OK 0x1000
#define MII_1000BT_STAT_LP_FDX_CAP 0x0800
#define MII_1000BT_STAT_LP_HDX_CAP 0x0400
#define CICADA_125MHZ_CLOCK_ENABLE 0x0001
#define MII_CICADA_DISABLE_ECHO_MODE 0x2000
#define MII_CICADA_MODE_SELECT_BITS 0xf000
#define MII_CICADA_MODE_SELECT_RGMII 0x1000
#define MII_CICADA_POWER_SUPPLY_BITS 0x0e00
#define MII_CICADA_POWER_SUPPLY_3_3V 0x0000
#define MII_CICADA_POWER_SUPPLY_2_5V 0x0200
#define MII_CICADA_PIN_PRORITY_SETTING 0x0004
#define MII_CICADA_PIN_PRORITY_DEFAULT 0x0000
#define NGE_REG_SIZE 0xfff
#define NGE_MII_SIZE 0x20
#define NGE_SEEROM_SIZE 0x800
/*
* Legacy rx's bd which does not support
* any hardware offload
*/
typedef struct _legacy_rx_bd {
union {
struct {
} cntl_bits;
} cntl_status;
/*
* Stand offload rx's bd which supports hareware checksum
*/
#define CK8G_NO_HSUM 0x0
#define CK8G_TCP_SUM_ERR 0x1
#define CK8G_UDP_SUM_ERR 0x2
#define CK8G_IP_HSUM_ERR 0x3
#define CK8G_IP_HSUM 0x4
#define CK8G_TCP_SUM 0x5
#define CK8G_UDP_SUM 0x6
#define CK8G_RESV 0x7
typedef struct _sum_rx_bd {
union {
struct {
} control_bits;
struct {
} status_bits;
} cntl_status;
} sum_rx_bd, *psum_rx_bd;
/*
* Hot offload rx's bd which support 64bit access and
* full-tcp hardware offload
*/
typedef struct _hot_rx_bd {
union {
struct {
} control_bits;
struct {
} cntl_status;
} hot_rx_bd, *phot_rx_bd;
/*
* Legacy tx's bd which does not support
* any hardware offload
*/
typedef struct _legacy_tx_bd {
union {
struct {
} control_bits;
struct {
} status_bits;
} cntl_status;
/*
* Stand offload tx's bd which supports hareware checksum
*/
typedef struct _sum_tx_bd {
union {
struct {
struct {
struct {
} status_bits;
} sum_tx_bd, *psum_tx_bd;
/*
* Hot offload tx's bd which support 64bit access and
* full-tcp hardware offload
*/
typedef struct _hot_tx_bd {
union {
struct {
} parm_bits;
} hot_parms;
union {
struct {
struct {
struct {
} status_bits;
} hot_tx_bd, *phot_tx_bd;
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NGE_CHIP_H */