/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NGE_CHIP_H
#define _SYS_NGE_CHIP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "nge.h"
typedef union _nge_interbus_conf {
struct {
} conf_bits;
/* Private PCI configuration register for MSI mask of mcp55 */
typedef union _nge_msi_mask_conf {
struct {
/* Private PCI configuration register for MSI map capability of mcp55 */
typedef union _nge_msi_map_cap_conf {
struct {
/*
* Master interrupt
*/
typedef union _nge_intr_src {
struct {
} int_bits;
} nge_intr_src;
/*
* Master interrupt Mask
*/
typedef union _nge_intr_mask {
struct {
} mask_bits;
/*
* Software timer control register
*/
typedef union _nge_swtr_cntl {
struct {
} cntl_bits;
/*
* Software Timer Interval
*/
/* Default timer interval, 97 would mean 1 ms */
typedef union _nge_itc {
struct {
} itc_bits;
} nge_itc;
/*
* Fatal error register
*/
typedef union _nge_reg010 {
struct {
} reg010_bits;
} nge_reg010;
/*
* MSI vector map register 0
*/
typedef union _nge_msi_map0_vec {
struct {
} vecs_bits;
/*
* MSI vector map register 1
*/
typedef union _nge_msi_map1_vec {
struct {
} vecs_bits;
/*
* MSI vector map register 2
*/
/*
* MSI vector map register 2
*/
/*
* MSI mask register for mcp55
*/
typedef union _nge_msi_mask {
struct {
/*
* Software misc register for mcp51
*/
typedef union _nge_soft_misc {
struct {
} misc_bits;
/*
* DMA configuration
*/
typedef union _nge_dma_cfg {
struct {
} cfg_bits;
} nge_dma_cfg;
/*
* Request DMA configuration
*/
typedef union _nge_dma_rcfg {
struct {
} rcfg_bis;
} nge_dma_rcfg;
/*
* Hot DMA configuration
*/
typedef union _nge_dma_hcfg {
struct {
} hcfg_bits;
} nge_dma_hcfg;
/*
* PMU control register 0 for mcp51
*/
typedef union _nge_pmu_cntl0 {
struct {
} cntl0_bits;
/*
* PMU control register 1 for mcp51
*/
typedef union _nge_pmu_cntl1 {
struct {
} cntl1_bits;
/*
* PMU control register 2 for mcp51
*/
typedef union _nge_pmu_cntl2 {
struct {
} cntl2_bits;
/*
* PMU core idle limit register for mcp51
*/
/*
* PMU device idle limit register for mcp51
*/
/*
* PMU core idle count value register for mcp51
*/
/*
* PMU device idle count value register for mcp51
*/
/*
* Transmit control
*/
typedef union _nge_tx_cntl {
struct {
} cntl_bits;
} nge_tx_cntl;
/*
* Transmit enable
* Note: for ck804 or mcp51, this is 8-bit register;
* for mcp55, it is a 32-bit register.
*/
typedef union _nge_tx_en {
struct {
} bits;
} nge_tx_en;
/*
* Transmit status
*/
typedef union _nge_tx_sta {
struct {
} sta_bits;
} nge_tx_sta;
/*
* Receive control
*/
typedef union _nge_rx_cntrl0 {
struct {
} cntl_bits;
/*
* Maximum receive Frame size
*/
typedef union _nge_rx_cntl1 {
struct {
} cntl_bits;
} nge_rx_cntl1;
/*
* Receive enable register
* Note: for ck804 and mcp51, this is a 8-bit register;
* for mcp55, it is a 32-bit register.
*/
typedef union _nge_rx_en {
struct {
} bits;
} nge_rx_en;
/*
* Receive status register
*/
typedef union _nge_rx_sta {
struct {
} sta_bits;
} nge_rx_sta;
/*
* Backoff Control
*/
typedef union _nge_bkoff_cntl {
struct {
} bkoff_bits;
/*
* Transmit defferral timing
*/
typedef union _nge_tx_def {
struct {
} def_bits;
} nge_tx_def;
/*
* Receive defferral timing
*/
typedef union _nge_rx_def {
struct {
} def_bits;
} nge_rx_def;
/*
* Low 32 bit unicast address
*/
union {
struct {
} addr_bits;
/*
* High 32 bit unicast address
*/
typedef union _nge_uni_addr1 {
struct {
} addr_bits;
/*
* Low 32 bit multicast address
*/
union {
struct {
/*
* High 32 bit multicast address
*/
typedef union _nge_mul_addr1 {
struct {
/*
* Low 32 bit multicast mask
*/
union {
struct {
} mask_bits;
/*
* High 32 bit multicast mask
*/
union {
struct {
} mask_bits;
/*
* Mac-to Phy Interface
*/
typedef union _nge_mac2phy {
struct {
} m2p_bits;
} nge_mac2phy;
/*
* Transmit Descriptor Ring address
*/
typedef union _nge_tx_addr {
struct {
} addr_bits;
} nge_tx_addr;
/*
* Receive Descriptor Ring address
*/
typedef union _nge_rx_addr {
struct {
} addr_bits;
} nge_rx_addr;
/*
*/
typedef union _nge_rxtx_dlen {
struct {
} dlen_bits;
/*
* Transmit polling register
*/
typedef union _nge_tx_poll {
struct {
} poll_bits;
} nge_tx_poll;
/*
* Receive polling register
*/
typedef union _nge_rx_poll {
struct {
} poll_bits;
} nge_rx_poll;
/*
* Transmit polling count
*/
union {
struct {
} cnt_bits;
} nge_tx_pcnt;
/*
* Receive polling count
*/
union {
struct {
} cnt_bits;
} nge_rx_pcnt;
/*
* Current tx's descriptor address
*/
union {
struct {
} addr_bits;
/*
* Current rx's descriptor address
*/
union {
struct {
} addr_bits;
/*
* Current tx's data buffer address
*/
union {
struct {
} prd0_bits;
/*
* Current tx's data buffer status
*/
union {
struct {
} prd1_bits;
/*
* Current rx's data buffer address
*/
union {
struct {
/*
* Current rx's data buffer status
*/
/*
* Next tx's descriptor address
*/
union {
struct {
/*
* Next rx's descriptor address
*/
union {
struct {
} addr_bits;
/*
* Transmit fifo watermark
*/
#define TX_FIFO_TBFW 0
typedef union _nge_tx_fifo_wm {
struct {
} wm_bits;
/*
* Receive fifo watermark
*/
typedef union _nge_rx_fifo_wm {
struct {
} wm_bits;
/*
* Chip mode control
*/
typedef union _nge_mode_cntl {
struct {
} mode_bits;
/*
* Mii interrupt register
* Note: for mcp55, this is a 32-bit register.
*/
typedef union _nge_mintr_src {
struct {
} src_bits;
/*
* Mii interrupt mask
* Note: for mcp55, this is a 32-bit register.
*/
typedef union _nge_mintr_mask {
struct {
} mask_bits;
/*
* Mii control and status
*/
typedef union _nge_mii_cs {
struct {
} cs_bits;
} nge_mii_cs;
/*
* Mii Clock timer register
*/
typedef union _nge_mii_tm {
struct {
} tm_bits;
} nge_mii_tm;
/*
* Mdio address
*/
typedef union _nge_mdio_adr {
struct {
} adr_bits;
} nge_mdio_adr;
/*
* Mdio data
*/
/*
* Power Management and Control
*/
typedef union _nge_pm_cntl {
struct {
/*
* mp_en: Magic Packet Enable
* pm_en: Pattern Match Enable
* lc_en: Link Change Enable
*/
} cntl_bits;
} nge_pm_cntl;
/*
* Seeprom control
*/
typedef union _nge_cp_cntl {
struct {
} cntl_bits;
} nge_cp_cntl;
/*
* Seeprom cmd control
*/
typedef union _nge_ep_cmd {
struct {
} cmd_bits;
} nge_ep_cmd;
/*
* Seeprom data register
*/
typedef union _nge_ep_data {
struct {
} data_bits;
} nge_ep_data;
/*
* Power management control 2nd register (since MCP51)
*/
typedef union _nge_pm_cntl2 {
struct {
} cntl_bits;
} nge_pm_cntl2;
/*
* ASF RAM 0x800-0xfff
*/
/*
* Hardware-defined Statistics Block Offsets
*
* These are given in the manual as addresses in NIC memory, starting
* from the NIC statistics area base address of 0x2000;
*/
typedef enum {
/*
* Hardware-defined Statistics Block
*
* Another view of the statistic block, as a array and a structure ...
*/
typedef union {
struct {
} s;
/*
*/
/*
* New bits in the MII_CONTROL register
*/
/*
* Bits in the MII_1000BASE_T_CONTROL register
*
* (otherwise, roles are automatically negotiated). When this bit is set,
* the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced.
*/
/*
* Bits in the MII_1000BASE_T_STATUS register
*/
/*
* Legacy rx's bd which does not support
* any hardware offload
*/
typedef struct _legacy_rx_bd {
union {
struct {
} cntl_bits;
} cntl_status;
/*
* Stand offload rx's bd which supports hareware checksum
*/
typedef struct _sum_rx_bd {
union {
struct {
} control_bits;
struct {
} status_bits;
} cntl_status;
/*
* Hot offload rx's bd which support 64bit access and
* full-tcp hardware offload
*/
typedef struct _hot_rx_bd {
union {
struct {
} control_bits;
struct {
} cntl_status;
/*
* Legacy tx's bd which does not support
* any hardware offload
*/
typedef struct _legacy_tx_bd {
union {
struct {
} control_bits;
struct {
} status_bits;
} cntl_status;
/*
* Stand offload tx's bd which supports hareware checksum
*/
typedef struct _sum_tx_bd {
union {
struct {
struct {
struct {
} status_bits;
/*
* Hot offload tx's bd which support 64bit access and
* full-tcp hardware offload
*/
typedef struct _hot_tx_bd {
union {
struct {
} parm_bits;
} hot_parms;
union {
struct {
struct {
struct {
} status_bits;
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NGE_CHIP_H */