nge_chip.h revision a01a4735489b25416b449c3231ab8b710caaeb1c
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d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
47693af92e50a1ad81825eb01b7157a211269613mx * Use is subject to license terms.
6f3e57ac9d0b054c3169579f3422080b8ba10105mxextern "C" {
a01a4735489b25416b449c3231ab8b710caaeb1cWinson Wang - Sun Microsystems - Beijing China#define DEVICE_ID_MCP77_760 0x760
6f3e57ac9d0b054c3169579f3422080b8ba10105mx/* Private PCI configuration register for bus config of ck804/mcp55 */
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_interbus_conf {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx/* Private PCI configuration register for MSI mask of mcp55 */
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_msi_mask_conf {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx/* Private PCI configuration register for MSI map capability of mcp55 */
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_msi_map_cap_conf {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Master interrupt
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_intr_src {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Master interrupt Mask
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_intr_mask {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Software timer control register
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_swtr_cntl {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Software Timer Interval
02d51d0d625c185ad277d9ad1ddf34b06f78b9b4jj/* Default timer interval, 97 would mean 1 ms */
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_itc {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Fatal error register
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_reg010 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * MSI vector map register 0
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_msi_map0_vec {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * MSI vector map register 1
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_msi_map1_vec {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * MSI vector map register 2
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * MSI vector map register 2
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * MSI mask register for mcp55
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_msi_mask {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Software misc register for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_soft_misc {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * DMA configuration
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_dma_cfg {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Request DMA configuration
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_dma_rcfg {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Hot DMA configuration
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_dma_hcfg {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PMU control register 0 for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_pmu_cntl0 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PMU control register 1 for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_pmu_cntl1 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PMU control register 2 for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_pmu_cntl2 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PMU core idle limit register for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PMU device idle limit register for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PMU core idle count value register for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PMU device idle count value register for mcp51
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit control
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_tx_cntl {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit enable
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Note: for ck804 or mcp51, this is 8-bit register;
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * for mcp55, it is a 32-bit register.
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China#define NGE_SMU_FREE 0x0
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China#define NGE_SMU_GET 0xf
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_tx_en {
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China uint32_t val;
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China uint32_t tx_en:1;
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China uint32_t resv1_7:7;
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China uint32_t smu2mac:4;
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China uint32_t mac2smu:4;
d635b452b5b58e50f0c67983f4a57a04deefce77Winson Wang - Sun Microsystems - Beijing China uint32_t resv16_31:16;
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit status
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_tx_sta {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive control
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_cntrl0 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Maximum receive Frame size
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_cntl1 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive enable register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Note: for ck804 and mcp51, this is a 8-bit register;
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * for mcp55, it is a 32-bit register.
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_en {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive status register
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_sta {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Backoff Control
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_bkoff_cntl {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit defferral timing
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_tx_def {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive defferral timing
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_def {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Low 32 bit unicast address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * High 32 bit unicast address
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_uni_addr1 {
d27d4a13eaba374ddedac2be3de8c5318360ca01Miles Xu, Sun Microsystems#define LOW_24BITS_MASK 0xffffffULL
d27d4a13eaba374ddedac2be3de8c5318360ca01Miles Xu, Sun Microsystems#define REVERSE_MAC_ELITE 0x211900ULL
d27d4a13eaba374ddedac2be3de8c5318360ca01Miles Xu, Sun Microsystems#define REVERSE_MAC_GIGABYTE 0xe61600ULL
d27d4a13eaba374ddedac2be3de8c5318360ca01Miles Xu, Sun Microsystems#define REVERSE_MAC_ASUS 0x601d00ULL
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Low 32 bit multicast address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * High 32 bit multicast address
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mul_addr1 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Low 32 bit multicast mask
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * High 32 bit multicast mask
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Mac-to Phy Interface
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mac2phy {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit Descriptor Ring address
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_tx_addr {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive Descriptor Ring address
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_addr {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Rx/tx descriptor ring leng
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Note: for mcp55, tdlen/rdlen are 14 bit.
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rxtx_dlen {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit polling register
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_tx_poll {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive polling register
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_poll {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit polling count
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive polling count
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Current tx's descriptor address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Current rx's descriptor address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Current tx's data buffer address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Current tx's data buffer status
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Current rx's data buffer address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Current rx's data buffer status
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Next tx's descriptor address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Next rx's descriptor address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Transmit fifo watermark
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_tx_fifo_wm {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Receive fifo watermark
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_rx_fifo_wm {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Chip mode control
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mode_cntl {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Mii interrupt register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Note: for mcp55, this is a 32-bit register.
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mintr_src {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Mii interrupt mask
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Note: for mcp55, this is a 32-bit register.
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mintr_mask {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Mii control and status
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mii_cs {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Mii Clock timer register
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mii_tm {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Mdio address
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_mdio_adr {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Mdio data
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Power Management and Control
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_pm_cntl {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * mp_en: Magic Packet Enable
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * pm_en: Pattern Match Enable
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * lc_en: Link Change Enable
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Seeprom control
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_cp_cntl {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Seeprom cmd control
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_ep_cmd {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Seeprom data register
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_ep_data {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Power management control 2nd register (since MCP51)
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union _nge_pm_cntl2 {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * ASF RAM 0x800-0xfff
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Hardware-defined Statistics Block Offsets
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * These are given in the manual as addresses in NIC memory, starting
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * from the NIC statistics area base address of 0x2000;
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef enum {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Hardware-defined Statistics Block
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Another view of the statistic block, as a array and a structure ...
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef union {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * MII (PHY) registers, beyond those already defined in <sys/miiregs.h>
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * New bits in the MII_CONTROL register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * New bits in the MII_AN_ADVERT register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Values for the <selector> field of the MII_AN_ADVERT register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Bits in the MII_1000BASE_T_CONTROL register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * The MASTER_CFG bit enables manual configuration of Master/Slave mode
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * (otherwise, roles are automatically negotiated). When this bit is set,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx#define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */
6f3e57ac9d0b054c3169579f3422080b8ba10105mx#define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Bits in the MII_1000BASE_T_STATUS register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Legacy rx's bd which does not support
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * any hardware offload
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef struct _legacy_rx_bd {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Stand offload rx's bd which supports hareware checksum
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef struct _sum_rx_bd {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Hot offload rx's bd which support 64bit access and
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * full-tcp hardware offload
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef struct _hot_rx_bd {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Legacy tx's bd which does not support
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * any hardware offload
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef struct _legacy_tx_bd {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Stand offload tx's bd which supports hareware checksum
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef struct _sum_tx_bd {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Hot offload tx's bd which support 64bit access and
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * full-tcp hardware offload
6f3e57ac9d0b054c3169579f3422080b8ba10105mxtypedef struct _hot_tx_bd {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx#endif /* _SYS_NGE_CHIP_H */