/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007-2009 Myricom, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _myri10ge_mcp_h
#define _myri10ge_mcp_h
#ifdef MXGEFW
#ifndef _stdint_h_
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef signed long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
#endif
#endif
/* 8 Bytes */
struct mcp_dma_addr {
};
/* 4 Bytes */
struct mcp_slot {
};
#ifdef MXGEFW_NDIS
/* 8-byte descriptor, exclusively used by NDIS drivers. */
struct mcp_slot_8 {
/* Place hash value at the top so it gets written before length.
* The driver polls length.
*/
};
/* Two bits of length in mcp_slot are used to indicate hash type. */
#endif
/* 64 Bytes */
struct mcp_cmd {
/* 8 */
/* 16 */
/* 24 */
};
/* 8 Bytes */
struct mcp_cmd_response {
};
/*
flags used in mcp_kreq_ether_send_t:
The SMALL flag is only needed in the first segment. It is raised
for packets that are total less or equal 512 bytes.
The CKSUM flag must be set in all segments.
The PADDED flags is set if the packet needs to be padded, and it
must be set for all segments.
The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
length of all previous segments was odd.
*/
union mcp_pso_or_cumlen {
};
/* 16 Bytes */
struct mcp_kreq_ether_send {
};
/* 8 Bytes */
struct mcp_kreq_ether_recv {
};
/* Commands */
enum myri10ge_mcp_cmd_type {
MXGEFW_CMD_NONE = 0,
/* Reset the mcp, it is left in a safe state, waiting
for the driver to set all its parameters */
/* get the version number of the current firmware..
(may be available in the eeprom strings..? */
/* Parameters which must be set by the driver before it can
issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
MXGEFW_CMD_RESET is issued */
/* data0 = LSW of the host address
* data1 = MSW of the host address
* data2 = slice number if multiple slices are used
*/
/* Parameters which refer to lanai SRAM addresses where the
driver must issue PIO writes for various things */
/* data0 = slice number if multiple slices are used */
/* Parameters which refer to rings stored on the MCP,
and whose size is controlled by the mcp */
/* Parameters which refer to rings stored in the host,
and whose size is controlled by the host. Note that
all must be physically contiguous and must contain
a power of 2 number of entries. */
/* command to bring ethernet interface up. Above parameters
(plus mtu & mac address) must have been exchanged prior
to issuing this command */
/* command to bring ethernet interface down. No further sends
or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
is issued, and all interrupt queues must be flushed prior
to ack'ing this command */
/* commands the driver may issue live, without resetting
the nic. Note that increasing the mtu "live" should
only be done if the driver has already supplied buffers
sufficiently large to handle the new mtu. Decreasing
the mtu live is safe */
/* do a DMA test
data0,data1 = DMA address
data2 = RDMA length (MSH), WDMA length (LSH)
command return data = repetitions (MSH), 0.5-ms ticks (LSH)
*/
/* returns MXGEFW_CMD_ERROR_MULTICAST
if there is no room in the cache
data0,MSH(data1) = multicast group address */
/* returns MXGEFW_CMD_ERROR_MULTICAST
if the address is not in the cache,
or is equal to FF-FF-FF-FF-FF-FF
data0,MSH(data1) = multicast group address */
/* data0, data1 = bus addr,
* data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
* adding new stuff to mcp_irq_data without changing the ABI
*
* If multiple slices are used, data2 contains both the size of the
* structure (in the lower 16 bits) and the slice number
* (in the upper 16 bits).
*/
/* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
chipset */
/* return data = boolean, true if the chipset is known to be unaligned */
/* data0 = number of big buffers to use. It must be 0 or a power of 2.
* 0 indicates that the NIC consumes as many buffers as they are required
* for packet. This is the default behavior.
* A power of 2 number indicates that the NIC always uses the specified
* number of buffers for each big receive packet.
* It is up to the driver to ensure that this value is big enough for
* the NIC to be able to receive maximum-sized packets.
*/
/* data0 = number of slices n (0, 1, ..., n-1) to enable
* data1 = interrupt mode | use of multiple transmit queues.
* 1=use one MSI-X per queue.
* If all queues share one interrupt, the driver must have set
* RSS_SHARED_INTERRUPT_DMA before enabling queues.
* 2=enable both receive and send queues.
* Without this bit set, only one send queue (slice 0's send queue)
* is enabled. The receive queues are always enabled.
*/
/* data0, data1 = bus address lsw, msw */
/* get the offset of the indirection table */
/* set the size of the indirection table */
/* get the offset of the secret key */
/* tell nic that the secret key's been updated */
* 0: disable rss. nic does not distribute receive packets.
* 1: enable rss. nic distributes receive packets among queues.
* data1 = hash type
* 1: IPV4 (required by RSS)
* 2: TCP_IPV4 (required by RSS)
* 3: IPV4 | TCP_IPV4 (required by RSS)
* 4: source port
* 5: source port + destination port
*/
/* Return data = the max. size of the entire headers of a IPv6 TSO packet.
* If the header size of a IPv6 TSO packet is larger than the specified
* value, then the driver must not use TSO.
* This size restriction only applies to IPv6 TSO.
* For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
* always has enough header buffer to store maximum-sized headers.
*/
/* data0 = TSO mode.
*/
#define MXGEFW_TSO_MODE_LINUX 0
/* Starts to get a fresh copy of one byte or of the module i2c table, the
* obtained data is cached inside the xaui-xfi chip :
* data0 : 0 => get one byte, 1=> get 256 bytes
* data1 : If data0 == 0: location to refresh
* bit 7:0 register location
* bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
* bit 23:16 is the i2c bus number (for multi-port NICs)
* If data0 == 1: unused
* The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
* During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
* will return MXGEFW_CMD_ERROR_BUSY
*/
/* Return the last obtained copy of a given byte in the xfp i2c table
* (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
* data0 : index of the desired table entry
* Return data = the byte stored at the requested index in the table
*/
/* Return data = NIC memory offset of mcp_vpump_public_global */
/* Resets the VPUMP state */
/* data0 = mcp_slot type to use.
* 0 = the default 4B mcp_slot
* 1 = 8B mcp_slot_8
*/
#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0
/* set the throttle factor for ethp_z8e
data0 = throttle_factor
throttle_factor = 256 * pcie-raw-speed / tx_speed
tx_speed = 256 * pcie-raw-speed / throttle_factor
For PCI-E x8: pcie-raw-speed == 16Gb/s
For PCI-E x4: pcie-raw-speed == 8Gb/s
ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
*/
/* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
/* Get the lanai clock */
/* offset of dca control for WDMAs */
/* VMWare NetQueue commands */
/* data0 = filter_id << 16 | queue << 8 | type */
/* data1 = MS4 of MAC Addr */
/* data2 = LS2_MAC << 16 | VLAN_tag */
/* data0 = filter_id */
/* When set, small receive buffers can cross page boundaries.
* Both small and big receive buffers may start at any address.
* This option has performance implications, so use with caution.
*/
};
enum myri10ge_mcp_cmd_status {
MXGEFW_CMD_OK = 0,
};
struct mcp_irq_data {
/* add new counters at the beginning */
/* 40 Bytes */
#define MXGEFW_LINK_DOWN 0
};
#ifdef MXGEFW_NDIS
/* Exclusively used by NDIS drivers */
struct mcp_rss_shared_interrupt {
};
#endif
/* definitions for NETQ filter type */
#define MXGEFW_NETQ_FILTERTYPE_NONE 0
#endif /* _myri10ge_mcp_h */