9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * CDDL HEADER START
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9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Common Development and Distribution License (the "License").
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * You may not use this file except in compliance with the License.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * See the License for the specific language governing permissions
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * and limitations under the License.
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9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * If applicable, add the following below this CDDL HEADER, with the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * fields enclosed by brackets "[]" replaced with your own identifying
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9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * CDDL HEADER END
c7facc54c4abed9e554ff80225311e6b7048d3c9Bill Taylor * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Use is subject to license terms.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Tavor Configuration Profile Routines
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Implements the routines necessary for initializing and (later) tearing
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * down the list of Tavor configuration information.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Set to enable alternative configurations: 0 = automatic config, 1 = manual */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported QPs and their maximum size */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_qp = TAVOR_NUM_QP_SHIFT_128;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_max_qp_sz = TAVOR_QP_SZ_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported SGL per WQE */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported CQs and their maximum size */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_cq = TAVOR_NUM_CQ_SHIFT_128;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_max_cq_sz = TAVOR_CQ_SZ_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Select to enable SRQ or not; NOTE: 0 for disabled, 1 for enabled */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported SRQs and their maximum size */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_srq = TAVOR_NUM_SRQ_SHIFT_128;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_max_srq_sz = TAVOR_SRQ_SZ_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Default size for all EQs */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported RDB (for incoming RDMA Read/Atomic) */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_rdb = TAVOR_NUM_RDB_SHIFT_128;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Number of support multicast groups, number of QP per multicast group, and
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the number of entries (from the total number) in the multicast group "hash
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_mcg = TAVOR_NUM_MCG_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_num_qp_per_mcg = TAVOR_NUM_QP_PER_MCG;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Number of supported MPTs (memory regions and windows) and their maximum
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * size. Also the number of MTT per "MTT segment" (see tavor_mr.h for more
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_mpt = TAVOR_NUM_MPT_SHIFT_128;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_128;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_mttseg = TAVOR_NUM_MTTSEG_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Number of supported Tavor mailboxes ("In" and "Out") and their maximum
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * sizes, respectively
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_intr_inmbox = TAVOR_NUM_INTR_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_intr_outmbox = TAVOR_NUM_INTR_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_inmbox_size = TAVOR_MBOX_SIZE_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported UAR pages */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_num_uar = TAVOR_NUM_UAR_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported Protection Domains (PD) */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported Address Handles (AH) */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Number of total supported PKeys per PKey table (i.e.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * per port). Also the number of SGID per GID table.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_log_max_gidtbl = TAVOR_NUM_GIDTBL_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Maximum "responder resources" (in) and "initiator depth" (out) per QP */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Maximum supported MTU and portwidth */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_max_port_width = TAVOR_MAX_PORT_WIDTH;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported Virtual Lanes (VL) */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor/* Number of supported ports (1 or 2) */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Whether or not to use the built-in (i.e. in firmware) agents for QP0 and
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * QP1, respectively.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Whether DMA mappings should be made with DDI_DMA_STREAMING or with
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * DDI_DMA_CONSISTENT mode. Note: 0 for "streaming", 1 for "consistent"
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * For DMA mappings made with DDI_DMA_CONSISTENT, this flag determines
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * whether to override the necessity for calls to ddi_dma_sync().
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Whether DMA mappings should bypass the PCI IOMMU or not.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * tavor_iommu_bypass is a global setting for all memory addresses. However,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * if set to BYPASS, memory attempted to be registered for streaming (ie:
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * NON-COHERENT) will necessarily turn off BYPASS for that registration. To
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * instead disable streaming in this situation the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * 'tavor_disable_streaming_on_bypass' can be set to 1. This setting will
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * change the memory mapping to be implicitly consistent (ie: COHERENT), and
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * will still perform the iommu BYPASS operation.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Whether QP work queues should be allocated from system memory or
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Whether SRQ work queues should be allocated from system memory or
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Whether Tavor should use MSI (Message Signaled Interrupts), if available.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Note: 0 indicates 'legacy interrupt', 1 indicates MSI (if available)
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * This is a patchable variable that determines the time we will wait after
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * initiating SW reset before we do our first read from Tavor config space.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * If this value is set too small (less than the default 100ms), it is
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * possible for Tavor hardware to be unready to respond to the config cycle
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * reads. This could cause master abort on the PCI bridge. Note: If
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * "tavor_sw_reset_delay" is set to zero, then no software reset of the Tavor
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * device will be attempted.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_sw_reset_delay = TAVOR_SW_RESET_DELAY;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * These are patchable variables for tavor command polling. The poll_delay is
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the number of usec to wait in-between calls to poll the 'go' bit. The
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * poll_max is the total number of usec to loop in waiting for the 'go' bit to
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_cmd_poll_delay = TAVOR_CMD_POLL_DELAY;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_cmd_poll_max = TAVOR_CMD_POLL_MAX;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * This is a patchable variable that determines the frequency with which
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the AckReq bit will be set in outgoing RC packets. The AckReq bit will be
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * set in at least every 2^tavor_qp_ackreq_freq packets (but at least once
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * per message, i.e. in the last packet). Tuning this value can increase
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * IB fabric utilization by cutting down on the number of unnecessary ACKs.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Tayloruint32_t tavor_qp_ackreq_freq = TAVOR_QP_ACKREQ_FREQ;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * This is a patchable variable that determines the default value for the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * maximum number of outstanding split transactions. The number of
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * outstanding split transations (i.e. PCI reads) has an affect on device
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * throughput. The value here should not be modified as it defines the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * default (least common denominator - one (1) PCI read) behavior that is
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * guaranteed to work, regardless of how the Tavor firmware has been
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * initialized. The format for this variable is the same as the corresponding
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * field in the "PCI-X Command Register".
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Default SPARC platforms to be 1 outstanding PCI read.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Default non-SPARC platforms to be the default as set in tavor firmware
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * number of outstanding PCI reads.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * This is a patchable variable that determines the default value for the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * maximum size of PCI read burst. This maximum size has an affect on
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * device throughput. The value here should not be modified as it defines
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the default (least common denominator - 512B read) behavior that is
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * guaranteed to work, regardless of how the Tavor device has been
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * initialized. The format for this variable is the same as the corresponding
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * field in the "PCI-X Command Register".
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Default SPARC platforms to be 512B read.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylorstatic void tavor_check_iommu_bypass(tavor_state_t *state,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Default non-SPARC platforms to be the default as set in tavor firmware.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylorstatic void tavor_cfg_wqe_sizes(tavor_cfg_profile_t *cp);
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylorstatic void tavor_cfg_prop_lookup(tavor_state_t *state,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * tavor_cfg_profile_init_phase1()
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Context: Only called from attach() path context
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylortavor_cfg_profile_init_phase1(tavor_state_t *state)
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Allocate space for the configuration profile structure
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp = (tavor_cfg_profile_t *)kmem_zalloc(sizeof (tavor_cfg_profile_t),
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Although most of the configuration is enabled in "phase2" of the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * cfg_profile_init, we have to setup the OUT mailboxes here, since
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * they are used immediately after this "phase1" completes. Check for
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * alt_config_enable, and set the values appropriately. Otherwise, the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * config profile is setup using the values based on the dimm size.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * While it is expected that the mailbox size and number will remain
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the same independent of dimm size, we separate it out here anyway
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * for completeness.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * We have to setup SRQ settings here because MOD_STAT_CFG must be
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * called before our call to QUERY_DEVLIM. If SRQ is enabled, then we
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * must enable it in the firmware so that the phase2 settings will have
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the right device limits.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_intr_outmbox = tavor_log_num_intr_outmbox;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_outmbox_size = tavor_log_outmbox_size;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_intr_inmbox = tavor_log_num_intr_inmbox;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor } else if (state->ts_cfg_profile_setting >= TAVOR_DDR_SIZE_256) {
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_128) {
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_MIN) {
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_outmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_outmbox_size = TAVOR_MBOX_SIZE_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_inmbox = TAVOR_NUM_MAILBOXES_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor TNF_PROBE_0(tavor_cfg_profile_invalid_dimmsz_fail,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Set default DMA mapping mode. Ensure consistency of flags
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * with both architecture type and other configuration flags.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_streaming_consistent = DDI_DMA_STREAMING;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Can't do both "streaming" and IOMMU bypass */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor TNF_PROBE_0(tavor_cfg_profile_streamingbypass_fail,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_streaming_consistent = DDI_DMA_CONSISTENT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_streaming_consistent = DDI_DMA_CONSISTENT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Determine whether to override ddi_dma_sync() */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_consistent_syncoverride = tavor_consistent_syncoverride;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Attach the configuration profile to Tavor softstate */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * tavor_cfg_profile_init_phase2()
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Context: Only called from attach() path context
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylortavor_cfg_profile_init_phase2(tavor_state_t *state)
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Read the configuration profile from Tavor softstate */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Verify the config profile setting. The 'setting' should already be
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * set, during a call to ddi_dev_regsize() to get the size of DDR
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * memory, or during a fallback to a smaller supported size. If it is
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * not set, we should not have reached this 'phase2'. So we assert
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * The automatic configuration override is the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * 'tavor_alt_config_enable' variable. If this is set, we no longer
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * use the DIMM size to enable the correct profile. Instead, all of
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the tavor config options at the top of this file are used directly.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * This allows customization for a user who knows what they are doing
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * to set tavor configuration values manually.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * If this variable is 0, we do automatic config for both 128MB and
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * 256MB DIMM sizes.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Initialize the configuration profile
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Determine WQE sizes from requested max SGLs */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_default_eq_sz = tavor_log_default_eq_sz;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_mcg_hash = tavor_log_num_mcg_hash;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_in_qp = tavor_hca_max_rdma_in_qp;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_out_qp = tavor_hca_max_rdma_out_qp;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor } else if (state->ts_cfg_profile_setting >= TAVOR_DDR_SIZE_256) {
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Initialize the configuration profile
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Determine WQE sizes from requested max SGLs */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_256;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_128) {
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Initialize the configuration profile
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Determine WQE sizes from requested max SGLs */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_128;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor } else if (state->ts_cfg_profile_setting == TAVOR_DDR_SIZE_MIN) {
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Initialize the configuration profile for minimal footprint.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Determine WQE sizes from requested max SGLs */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_default_eq_sz = TAVOR_DEFAULT_EQ_SZ_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_num_qp_per_mcg = TAVOR_NUM_QP_PER_MCG_MIN;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_mcg_hash = TAVOR_NUM_MCG_HASH_SHIFT_MIN;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_max_mrw_sz = TAVOR_MAX_MEM_MPT_SHIFT_MIN;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_num_mttseg = TAVOR_NUM_MTTSEG_SHIFT_MIN;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_log_max_pkeytbl = TAVOR_NUM_PKEYTBL_SHIFT;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_in_qp = TAVOR_HCA_MAX_RDMA_IN_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_hca_max_rdma_out_qp = TAVOR_HCA_MAX_RDMA_OUT_QP;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp0_agents_in_fw = tavor_qp0_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_qp1_agents_in_fw = tavor_qp1_agents_in_fw;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_out_splt_trans = tavor_max_out_splt_trans;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_max_mem_rd_byte_cnt = tavor_max_mem_rd_byte_cnt;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor TNF_PROBE_0(tavor_cfg_profile_invalid_dimmsz_fail,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Set IOMMU bypass or not. Ensure consistency of flags with
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * architecture type.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Set whether QP WQEs will be in DDR or not */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor TAVOR_QUEUE_LOCATION_NORMAL : TAVOR_QUEUE_LOCATION_INDDR;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Set whether SRQ WQEs will be in DDR or not */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_srq_wq_inddr = (tavor_srq_wq_inddr == 0) ?
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor TAVOR_QUEUE_LOCATION_NORMAL : TAVOR_QUEUE_LOCATION_INDDR;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cp->cp_use_msi_if_avail = tavor_use_msi_if_avail;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Determine additional configuration from optional properties */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * tavor_cfg_profile_fini()
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Context: Only called from attach() and/or detach() path contexts
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Free up the space for configuration profile
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor kmem_free(state->ts_cfg_profile, sizeof (tavor_cfg_profile_t));
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * tavor_cfg_wqe_sizes()
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Context: Only called from attach() path context
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Get the requested maximum number SGL per WQE from the Tavor
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * patchable variable
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Use requested maximum number of SGL to calculate the max descriptor
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * size (while guaranteeing that the descriptor size is a power-of-2
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * cachelines). We have to use the calculation for QP1 MLX transport
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * because the possibility that we might need to inline a GRH, along
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * with all the other headers and alignment restrictions, sets the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * maximum for the number of SGLs that we can advertise support for.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor max_size = (TAVOR_QP_WQE_MLX_QP1_HDRS + (max_sgl << 4));
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Now clip the maximum descriptor size based on Tavor HW maximum
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor max_size = min(max_size, TAVOR_QP_WQE_MAX_SIZE);
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Then use the calculated max descriptor size to determine the "real"
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * maximum SGL (the number beyond which we would roll over to the next
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * power-of-2).
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor real_max_sgl = (max_size - TAVOR_QP_WQE_MLX_QP1_HDRS) >> 4;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Then save away this configuration information */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* SRQ SGL gets set to it's own patchable variable value */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * tavor_cfg_prop_lookup()
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Context: Only called from attach() path context
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylortavor_cfg_prop_lookup(tavor_state_t *state, tavor_cfg_profile_t *cp)
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Read the property defining the number of Tavor ports to
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * support. If the property is undefined or invalid, then return.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * We return here assuming also that OBP is not supposed to be setting
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * up other properties in this case (eg: HCA plugin cards). But if
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * this property is valid, then we print out a message for the other
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * properties to show an OBP error.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor num_ports = ddi_prop_get_int(DDI_DEV_T_ANY, state->ts_dip,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor if ((num_ports > TAVOR_NUM_PORTS) || (num_ports == 0)) {
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * The system image guid is not currently supported in the 1275
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * binding. So we leave this commented out for now.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Read the property defining the value to use later to override the
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * default SystemImageGUID (in firmware). If the property is
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * undefined, then return.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, state->ts_dip,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor DDI_PROP_DONTPASS, "system-image-guid", &datap, &nelementsp);
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor "Unable to read OBP system-image-guid property");
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Read the property defining the value to use later to override
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * the default SystemImageGUID (in firmware). If the property is
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * undefined, then return.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, state->ts_dip,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor DDI_PROP_DONTPASS, "node-guid", &datap, &nelementsp);
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cmn_err(CE_NOTE, "Unable to read OBP node-guid property");
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Using the value for the number of ports (above) read the properties
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * used to later to override the default PortGUIDs for each Tavor port.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * If either of these properties are undefined, then return.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor state->ts_dip, DDI_PROP_DONTPASS, "port-2-guid", &datap,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor "Unable to read OBP port-2-guid property");
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor status = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, state->ts_dip,
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor DDI_PROP_DONTPASS, "port-1-guid", &datap, &nelementsp);
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor cmn_err(CE_NOTE, "Unable to read OBP port-1-guid property");
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * tavor_check_iommu_bypass()
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Context: Only called from attach() path context
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylortavor_check_iommu_bypass(tavor_state_t *state, tavor_cfg_profile_t *cp)
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor /* Try mapping for IOMMU bypass (Force Physical) */
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor dma_attr.dma_attr_flags = DDI_DMA_FORCE_PHYSICAL;
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * Call ddi_dma_alloc_handle(). If this returns DDI_DMA_BADATTR then
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * it is not possible to use IOMMU bypass with our PCI bridge parent.
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * For example, certain versions of Tomatillo do not support IOMMU
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * bypass. Since the function we are in can only be called if iommu
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * bypass was requested in the config profile, we configure for bypass
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * if the ddi_dma_alloc_handle() was successful. Otherwise, we
9e39c5ba00a55fa05777cc94b148296af305e135Bill Taylor * configure for non-bypass (ie: normal) mapping.