/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
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*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
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*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
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*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Tavor Configuration Profile Routines
*
* Implements the routines necessary for initializing and (later) tearing
* down the list of Tavor configuration information.
*/
#include <sys/sysmacros.h>
/* Set to enable alternative configurations: 0 = automatic config, 1 = manual */
/* Number of supported QPs and their maximum size */
/* Number of supported SGL per WQE */
/* Number of supported CQs and their maximum size */
/* Select to enable SRQ or not; NOTE: 0 for disabled, 1 for enabled */
/* Number of supported SRQs and their maximum size */
/* Default size for all EQs */
/*
* Number of support multicast groups, number of QP per multicast group, and
* the number of entries (from the total number) in the multicast group "hash
* table"
*/
/*
* Number of supported MPTs (memory regions and windows) and their maximum
* size. Also the number of MTT per "MTT segment" (see tavor_mr.h for more
* details)
*/
/*
* Number of supported Tavor mailboxes ("In" and "Out") and their maximum
* sizes, respectively
*/
/* Number of supported UAR pages */
/* Number of supported Protection Domains (PD) */
/* Number of supported Address Handles (AH) */
/*
* Number of total supported PKeys per PKey table (i.e.
* per port). Also the number of SGID per GID table.
*/
/* Maximum "responder resources" (in) and "initiator depth" (out) per QP */
/* Maximum supported MTU and portwidth */
/* Number of supported Virtual Lanes (VL) */
/* Number of supported ports (1 or 2) */
/*
* Whether or not to use the built-in (i.e. in firmware) agents for QP0 and
* QP1, respectively.
*/
/*
* Whether DMA mappings should be made with DDI_DMA_STREAMING or with
* DDI_DMA_CONSISTENT mode. Note: 0 for "streaming", 1 for "consistent"
*/
/*
* For DMA mappings made with DDI_DMA_CONSISTENT, this flag determines
* whether to override the necessity for calls to ddi_dma_sync().
*/
/*
* Whether DMA mappings should bypass the PCI IOMMU or not.
* tavor_iommu_bypass is a global setting for all memory addresses. However,
* if set to BYPASS, memory attempted to be registered for streaming (ie:
* NON-COHERENT) will necessarily turn off BYPASS for that registration. To
* instead disable streaming in this situation the
* 'tavor_disable_streaming_on_bypass' can be set to 1. This setting will
* change the memory mapping to be implicitly consistent (ie: COHERENT), and
* will still perform the iommu BYPASS operation.
*/
/*
* Whether QP work queues should be allocated from system memory or
* from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
*/
/*
* Whether SRQ work queues should be allocated from system memory or
* from Tavor DDR memory. Note: 0 for system memory, 1 for DDR memory
*/
/*
* Whether Tavor should use MSI (Message Signaled Interrupts), if available.
* Note: 0 indicates 'legacy interrupt', 1 indicates MSI (if available)
*/
/*
* This is a patchable variable that determines the time we will wait after
* initiating SW reset before we do our first read from Tavor config space.
* If this value is set too small (less than the default 100ms), it is
* possible for Tavor hardware to be unready to respond to the config cycle
* reads. This could cause master abort on the PCI bridge. Note: If
* "tavor_sw_reset_delay" is set to zero, then no software reset of the Tavor
* device will be attempted.
*/
/*
* These are patchable variables for tavor command polling. The poll_delay is
* the number of usec to wait in-between calls to poll the 'go' bit. The
* poll_max is the total number of usec to loop in waiting for the 'go' bit to
* clear.
*/
/*
* This is a patchable variable that determines the frequency with which
* the AckReq bit will be set in outgoing RC packets. The AckReq bit will be
* set in at least every 2^tavor_qp_ackreq_freq packets (but at least once
* per message, i.e. in the last packet). Tuning this value can increase
* IB fabric utilization by cutting down on the number of unnecessary ACKs.
*/
/*
* This is a patchable variable that determines the default value for the
* maximum number of outstanding split transactions. The number of
* outstanding split transations (i.e. PCI reads) has an affect on device
* throughput. The value here should not be modified as it defines the
* default (least common denominator - one (1) PCI read) behavior that is
* guaranteed to work, regardless of how the Tavor firmware has been
* initialized. The format for this variable is the same as the corresponding
* field in the "PCI-X Command Register".
*/
#ifdef __sparc
/*
* Default SPARC platforms to be 1 outstanding PCI read.
*/
int tavor_max_out_splt_trans = 0;
#else
/*
* Default non-SPARC platforms to be the default as set in tavor firmware
* number of outstanding PCI reads.
*/
#endif
/*
* This is a patchable variable that determines the default value for the
* maximum size of PCI read burst. This maximum size has an affect on
* device throughput. The value here should not be modified as it defines
* the default (least common denominator - 512B read) behavior that is
* guaranteed to work, regardless of how the Tavor device has been
* initialized. The format for this variable is the same as the corresponding
* field in the "PCI-X Command Register".
*/
#ifdef __sparc
/*
* Default SPARC platforms to be 512B read.
*/
int tavor_max_mem_rd_byte_cnt = 0;
#else
/*
* Default non-SPARC platforms to be the default as set in tavor firmware.
*
*/
#endif
/*
* tavor_cfg_profile_init_phase1()
* Context: Only called from attach() path context
*/
int
{
/*
* Allocate space for the configuration profile structure
*/
KM_SLEEP);
cp->cp_fmr_enable = 0;
cp->cp_fmr_max_remaps = 0;
/*
* Although most of the configuration is enabled in "phase2" of the
* cfg_profile_init, we have to setup the OUT mailboxes here, since
* they are used immediately after this "phase1" completes. Check for
* alt_config_enable, and set the values appropriately. Otherwise, the
* config profile is setup using the values based on the dimm size.
* While it is expected that the mailbox size and number will remain
* the same independent of dimm size, we separate it out here anyway
* for completeness.
*
* We have to setup SRQ settings here because MOD_STAT_CFG must be
* called before our call to QUERY_DEVLIM. If SRQ is enabled, then we
* must enable it in the firmware so that the phase2 settings will have
* the right device limits.
*/
if (tavor_alt_config_enable) {
} else {
TAVOR_TNF_ERROR, "");
return (DDI_FAILURE);
}
/*
* Set default DMA mapping mode. Ensure consistency of flags
* with both architecture type and other configuration flags.
*/
if (tavor_streaming_consistent == 0) {
#ifdef __sparc
/* Can't do both "streaming" and IOMMU bypass */
if (tavor_iommu_bypass != 0) {
TAVOR_TNF_ERROR, "");
return (DDI_FAILURE);
}
#else
#endif
} else {
}
/* Determine whether to override ddi_dma_sync() */
/* Attach the configuration profile to Tavor softstate */
return (DDI_SUCCESS);
}
/*
* tavor_cfg_profile_init_phase2()
* Context: Only called from attach() path context
*/
int
{
/* Read the configuration profile from Tavor softstate */
/*
* Verify the config profile setting. The 'setting' should already be
* set, during a call to ddi_dev_regsize() to get the size of DDR
* memory, or during a fallback to a smaller supported size. If it is
* not set, we should not have reached this 'phase2'. So we assert
* here.
*/
/*
* The automatic configuration override is the
* 'tavor_alt_config_enable' variable. If this is set, we no longer
* use the DIMM size to enable the correct profile. Instead, all of
* the tavor config options at the top of this file are used directly.
*
* This allows customization for a user who knows what they are doing
* to set tavor configuration values manually.
*
* If this variable is 0, we do automatic config for both 128MB and
* 256MB DIMM sizes.
*/
if (tavor_alt_config_enable) {
/*
* Initialize the configuration profile
*/
/* Determine WQE sizes from requested max SGLs */
/*
* Initialize the configuration profile
*/
/* Determine WQE sizes from requested max SGLs */
/*
* Initialize the configuration profile
*/
/* Determine WQE sizes from requested max SGLs */
/*
* Initialize the configuration profile for minimal footprint.
*/
/* Determine WQE sizes from requested max SGLs */
} else {
TAVOR_TNF_ERROR, "");
return (DDI_FAILURE);
}
/*
* Set IOMMU bypass or not. Ensure consistency of flags with
* architecture type.
*/
#ifdef __sparc
if (tavor_iommu_bypass == 1) {
} else {
}
#else
#endif
/* Set whether QP WQEs will be in DDR or not */
/* Set whether SRQ WQEs will be in DDR or not */
/* Determine additional configuration from optional properties */
return (DDI_SUCCESS);
}
/*
* tavor_cfg_profile_fini()
*/
void
{
/*
* Free up the space for configuration profile
*/
}
/*
* tavor_cfg_wqe_sizes()
* Context: Only called from attach() path context
*/
static void
{
/*
* Get the requested maximum number SGL per WQE from the Tavor
* patchable variable
*/
/*
* Use requested maximum number of SGL to calculate the max descriptor
* size (while guaranteeing that the descriptor size is a power-of-2
* cachelines). We have to use the calculation for QP1 MLX transport
* because the possibility that we might need to inline a GRH, along
* with all the other headers and alignment restrictions, sets the
* maximum for the number of SGLs that we can advertise support for.
*/
}
/*
* Now clip the maximum descriptor size based on Tavor HW maximum
*/
/*
* Then use the calculated max descriptor size to determine the "real"
* maximum SGL (the number beyond which we would roll over to the next
* power-of-2).
*/
/* Then save away this configuration information */
/* SRQ SGL gets set to it's own patchable variable value */
}
/*
* tavor_cfg_prop_lookup()
* Context: Only called from attach() path context
*/
static void
{
int status;
/*
* Read the property defining the number of Tavor ports to
* support. If the property is undefined or invalid, then return.
* We return here assuming also that OBP is not supposed to be setting
* up other properties in this case (eg: HCA plugin cards). But if
* this property is valid, then we print out a message for the other
* properties to show an OBP error.
*/
DDI_PROP_DONTPASS, "#ports", 0);
return;
}
/*
* The system image guid is not currently supported in the 1275
* binding. So we leave this commented out for now.
*/
#ifdef SUPPORTED_IN_1275_BINDING
/*
* Read the property defining the value to use later to override the
* default SystemImageGUID (in firmware). If the property is
* undefined, then return.
*/
if (status == DDI_PROP_SUCCESS) {
} else {
"Unable to read OBP system-image-guid property");
}
#endif
/*
* Read the property defining the value to use later to override
* the default SystemImageGUID (in firmware). If the property is
* undefined, then return.
*/
if (status == DDI_PROP_SUCCESS) {
} else {
}
/*
* Using the value for the number of ports (above) read the properties
* used to later to override the default PortGUIDs for each Tavor port.
* If either of these properties are undefined, then return.
*/
if (num_ports == TAVOR_NUM_PORTS) {
&nelementsp);
if (status == DDI_PROP_SUCCESS) {
} else {
"Unable to read OBP port-2-guid property");
}
}
if (status == DDI_PROP_SUCCESS) {
} else {
}
}
#ifdef __sparc
/*
* tavor_check_iommu_bypass()
* Context: Only called from attach() path context
*/
static void
{
int status;
/* Try mapping for IOMMU bypass (Force Physical) */
/*
* Call ddi_dma_alloc_handle(). If this returns DDI_DMA_BADATTR then
* it is not possible to use IOMMU bypass with our PCI bridge parent.
* For example, certain versions of Tomatillo do not support IOMMU
* bypass. Since the function we are in can only be called if iommu
* bypass was requested in the config profile, we configure for bypass
* if the ddi_dma_alloc_handle() was successful. Otherwise, we
* configure for non-bypass (ie: normal) mapping.
*/
if (status == DDI_DMA_BADATTR) {
} else {
if (status == DDI_SUCCESS) {
}
}
}
#endif