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/*$FreeBSD: head/sys/dev/ixl/i40e_type.h 284049 2015-06-05 22:52:42Z jfv $*/
#ifndef _I40E_TYPE_H_
#define _I40E_TYPE_H_
#include "i40e_status.h"
#include "i40e_osdep.h"
#include "i40e_register.h"
#include "i40e_adminq.h"
#include "i40e_hmc.h"
#include "i40e_lan_hmc.h"
#include "i40e_devids.h"
#define UNREFERENCED_XPARAMETER
#ifndef I40E_MASK
/* I40E_MASK is a macro used on 32 bit registers */
#endif
/* something less than 1 minute */
/* Max default timeout in ms, */
/* Check whether address is multicast. */
/* Check whether an address is broadcast. */
/* Switch from ms to the 1usec global time (this is the GTIME resolution) */
/* forward declaration */
struct i40e_hw;
/* Data type manipulation macros. */
/* Number of Transmit Descriptors must be a multiple of 8. */
/* Number of Receive Descriptors must be a multiple of 32 if
* the number of descriptors is greater than 32.
*/
#define I40E_DESC_UNUSED(R) \
/* bitfields for Tx queue mapping in QTX_CTL */
/* debug masks - set these bits in hw->debug_mask to control output */
enum i40e_debug_mask {
/*
* Ugggh, have to cast these because of enums being "int" and these
* overflow int.
*/
};
/* PCI Bus Info */
/* Memory types */
enum i40e_memset_type {
I40E_NONDMA_MEM = 0,
};
/* Memcpy types */
enum i40e_memcpy_type {
};
/* These are structs for managing the hardware information and the operations.
* The structures of function pointers are filled out at init time when we
* know for sure exactly which hardware we're working with. This gives us the
* flexibility of using the same main driver code but adapting to slightly
* different hardware needs as new parts are developed. For this architecture,
* the Firmware and AdminQ are intended to insulate the driver from most of the
* future changes, but these structures will also do part of the job.
*/
enum i40e_mac_type {
I40E_MAC_UNKNOWN = 0,
#ifdef X722_SUPPORT
#endif
};
enum i40e_media_type {
};
enum i40e_fc_mode {
I40E_FC_NONE = 0,
};
enum i40e_set_fc_aq_failures {
};
enum i40e_vsi_type {
I40E_VSI_MAIN = 0,
};
enum i40e_queue_type {
I40E_QUEUE_TYPE_RX = 0,
};
struct i40e_link_status {
/* is Link Status Event notification to SW enabled */
bool lse_enable;
bool crc_enable;
/* 1st byte: module identifier */
/* 2nd byte: ethernet compliance codes for 10/40G */
/* 3rd byte: ethernet compliance codes for 1G */
};
};
struct i40e_phy_info {
bool get_link_info;
/* all the phy types the NVM is capable of */
};
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
/* Capabilities of a PF or a VF or the whole device */
struct i40e_hw_capabilities {
bool sr_iov_1_1;
bool vmdq;
bool dcb;
bool fcoe;
bool flex10_enable;
bool flex10_capable;
bool mgmt_cem;
bool ieee_1588;
bool iwarp;
bool fd;
bool rss;
};
struct i40e_mac_info {
};
enum i40e_aq_resources_ids {
};
enum i40e_aq_resource_access_type {
};
struct i40e_nvm_info {
};
/* definitions used in NVM update support */
enum i40e_nvmupd_cmd {
};
enum i40e_nvmupd_state {
};
* application, core driver, and shared code. Where is the right file?
*/
struct i40e_nvm_access {
};
/* PCI bus types */
enum i40e_bus_type {
};
/* PCI bus speeds */
enum i40e_bus_speed {
};
/* PCI bus widths */
enum i40e_bus_width {
};
/* Bus parameters */
struct i40e_bus_info {
};
/* Flow control (FC) parameters */
struct i40e_fc_info {
};
/* CEE or IEEE 802.1Qaz ETS Configuration data */
struct i40e_dcb_ets_config {
};
/* CEE or IEEE 802.1Qaz PFC Configuration data */
struct i40e_dcb_pfc_config {
};
/* CEE or IEEE 802.1Qaz Application Priority data */
struct i40e_dcb_app_priority_table {
};
struct i40e_dcbx_config {
};
/* Port hardware description */
struct i40e_hw {
void *back;
/* subsystem structs */
/* pci info */
bool adapter_stopped;
/* capabilities for entire device and PCI func */
/* Flow Director shared filter space */
/* device profile info */
/* for multi-function MACs */
/* Closest numa node to the device */
/* Admin Queue info */
/* state of nvm update process */
/* HMC info */
/* DCBX info */
/* debug mask */
};
{
#ifdef X722_SUPPORT
#else
#endif
}
struct i40e_driver_version {
};
/* RX Descriptors */
union i40e_16byte_rx_desc {
struct {
} read;
struct {
struct {
struct {
union {
} mirr_fcoe;
} lo_dword;
union {
} hi_dword;
} qword0;
struct {
} qword1;
};
union i40e_32byte_rx_desc {
struct {
/* bit 0 of hdr_buffer_addr is DD bit */
} read;
struct {
struct {
struct {
union {
} mirr_fcoe;
} lo_dword;
union {
/* Flow director filter id in case of
* Programming status desc WB
*/
} hi_dword;
} qword0;
struct {
} qword1;
struct {
} qword2;
struct {
union {
} lo_dword;
union {
} hi_dword;
} qword3;
};
#define I40E_RXD_QW0_FCOEINDX_SHIFT 0
enum i40e_rx_desc_status_bits {
/* Note: These are predefined bit offsets */
#ifdef X722_SUPPORT
#else
#endif
#ifdef X722_SUPPORT
#else
#endif
};
#define I40E_RXD_QW1_STATUS_SHIFT 0
enum i40e_rx_desc_fltstat_values {
};
#define I40E_RXD_PACKET_TYPE_UNICAST 0
enum i40e_rx_desc_error_bits {
/* Note: These are predefined bit offsets */
};
};
/* Packet type non-ip values */
enum i40e_rx_l2_ptype {
};
struct i40e_rx_ptype_decoded {
};
enum i40e_rx_ptype_outer_ip {
};
enum i40e_rx_ptype_outer_ip_ver {
};
};
enum i40e_rx_ptype_tunnel_type {
};
};
enum i40e_rx_ptype_inner_prot {
};
enum i40e_rx_ptype_payload_layer {
};
#define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
enum i40e_rx_desc_ext_status_bits {
/* Note: These are predefined bit offsets */
};
#define I40E_RXD_QW2_L2TAG2_SHIFT 0
enum i40e_rx_desc_pe_status_bits {
/* Note: These are predefined bit offsets */
};
/* Note: These are predefined bit offsets */
};
};
/* Note: These are predefined bit offsets */
};
/* TX Descriptor */
struct i40e_tx_desc {
};
#define I40E_TXD_QW1_DTYPE_SHIFT 0
enum i40e_tx_desc_dtype_value {
};
enum i40e_tx_desc_cmd_bits {
};
enum i40e_tx_desc_length_fields {
/* Note: These are predefined bit offsets */
};
/* Context descriptors */
struct i40e_tx_context_desc {
};
#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
enum i40e_tx_ctx_desc_cmd_bits {
};
#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
};
#ifdef X722_SUPPORT
#endif
struct i40e_nop_desc {
};
#define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
enum i40e_tx_nop_desc_cmd_bits {
/* Note: These are predefined bit offsets */
};
struct i40e_filter_program_desc {
};
#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
/* Packet Classifier Types for filters */
enum i40e_filter_pctype {
#ifdef X722_SUPPORT
/* Note: Values 0-28 are reserved for future use.
* Value 29, 30, 32 are not supported on XL710 and X710.
*/
#else
/* Note: Values 0-30 are reserved for future use */
#endif
#ifdef X722_SUPPORT
#else
/* Note: Value 32 is reserved for future use */
#endif
#ifdef X722_SUPPORT
/* Note: Values 37-38 are reserved for future use.
* Value 39, 40, 42 are not supported on XL710 and X710.
*/
#else
/* Note: Values 37-40 are reserved for future use */
#endif
#ifdef X722_SUPPORT
#endif
/* Note: Value 47 is reserved for future use */
/* Note: Values 51-62 are reserved for future use */
};
};
};
#define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
};
#ifdef X722_SUPPORT
#endif
enum i40e_filter_type {
};
struct i40e_vsi_context {
};
struct i40e_veb_context {
};
/* Statistics collected by each port, VSI, VEB, and S-channel */
struct i40e_eth_stats {
};
/* Statistics collected per VEB per TC */
struct i40e_veb_tc_stats {
};
/* Statistics collected by the MAC */
struct i40e_hw_port_stats {
/* eth stats collected by the port */
/* additional port specific stats */
/* flow director stats */
/* EEE LPI */
};
/* Checksum and Shadow RAM pointers */
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
/* Shadow RAM related */
/* Checksum should be calculated such that after adding all the words,
* including the checksum word itself, the sum should be 0xBABA.
*/
enum i40e_switch_element_types {
};
/* Supported EtherType filters */
enum i40e_ether_type_index {
I40E_ETHER_TYPE_1588 = 0,
};
/* Filter context base size is 1K */
/* Supported Hash filter values */
enum i40e_hash_filter_size {
};
/* DMA context base size is 0.5K */
/* Supported DMA context values */
enum i40e_dma_cntx_size {
};
/* Supported Hash look up table (LUT) sizes */
enum i40e_hash_lut_size {
};
/* Structure to hold a per PF filter control settings */
struct i40e_filter_control_settings {
/* number of PE Quad Hash filter buckets */
/* number of PE Quad Hash contexts */
/* number of FCoE filter buckets */
/* number of FCoE DDP contexts */
/* size of the Hash LUT */
/* enable FDIR filters for PF and its VFs */
bool enable_fdir;
/* enable Ethertype filters for PF and its VFs */
bool enable_ethtype;
bool enable_macvlan;
};
/* Structure to hold device level control filter counts */
struct i40e_control_filter_stats {
};
enum i40e_reset_type {
I40E_RESET_POR = 0,
};
/* IEEE 802.1AB LLDP Agent Variables from NVM */
struct i40e_lldp_variables {
};
/* Offsets into Alternate Ram */
/* Alternate Ram Bandwidth Masks */
/* RSS Hash Table Size */
/* PBA length (and one with additional zero-padding byte), see Table 6-2. */
#endif /* _I40E_TYPE_H_ */