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/*$FreeBSD: head/sys/dev/ixl/i40e_nvm.c 284049 2015-06-05 22:52:42Z jfv $*/
#include "i40e_prototype.h"
bool last_command);
/**
* i40e_init_nvm_ops - Initialize NVM function pointers
* @hw: pointer to the HW structure
*
* Setup the function pointers and the NVM info structure. Should be called
* once per NVM initialization, e.g. inside the i40e_init_shared_code().
* Please notice that the NVM term is used here (& in all methods covered
* in this file) as an equivalent of the FLASH part mapped into the SR.
* We are accessing FLASH always thru the Shadow RAM.
**/
{
DEBUGFUNC("i40e_init_nvm");
/* The SR size is stored regardless of the nvm programming mode
* as the blank mode may be used in the factory line.
*/
/* Switching to words (sr_size contains power of 2KB) */
/* Check if we are in the normal or blank NVM programming mode */
/* Max NVM timeout */
} else { /* Blank programming mode */
}
return ret_code;
}
/**
* i40e_acquire_nvm - Generic request for acquiring the NVM ownership
* @hw: pointer to the HW structure
* @access: NVM access type (read or write)
*
* This function will request NVM ownership for reading
* via the proper Admin Command.
**/
{
DEBUGFUNC("i40e_acquire_nvm");
/* Reading the Global Device Timer */
/* Store the timeout */
if (ret_code)
"NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
/* Poll until the current NVM owner timeouts */
i40e_msec_delay(10);
NULL);
if (ret_code == I40E_SUCCESS) {
break;
}
}
if (ret_code != I40E_SUCCESS) {
"NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
}
}
return ret_code;
}
/**
* i40e_release_nvm - Generic request for releasing the NVM ownership
* @hw: pointer to the HW structure
*
* This function will release NVM resource via the proper Admin Command.
**/
{
DEBUGFUNC("i40e_release_nvm");
return;
/* there are some rare cases when trying to release the resource
* results in an admin Q timeout, so handle them correctly
*/
while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
i40e_msec_delay(1);
I40E_NVM_RESOURCE_ID, 0, NULL);
total_delay++;
}
}
/**
* i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
* @hw: pointer to the HW structure
*
* Polls the SRCTL Shadow RAM register done bit.
**/
{
DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
/* Poll the I40E_GLNVM_SRCTL until the done bit is set */
if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
break;
}
i40e_usec_delay(5);
}
if (ret_code == I40E_ERR_TIMEOUT)
return ret_code;
}
/**
* i40e_read_nvm_word - Reads Shadow RAM
* @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
* @data: word read from the Shadow RAM
*
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
**/
{
#ifdef X722_SUPPORT
#endif
}
/**
* i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
* @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
* @data: word read from the Shadow RAM
*
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
**/
{
DEBUGFUNC("i40e_read_nvm_word_srctl");
"NVM read error: Offset %d beyond Shadow RAM limit %d\n",
goto read_nvm_exit;
}
/* Poll the done bit first */
if (ret_code == I40E_SUCCESS) {
/* Write the address and start reading */
/* Poll I40E_GLNVM_SRCTL until the done bit is set */
if (ret_code == I40E_SUCCESS) {
}
}
if (ret_code != I40E_SUCCESS)
"NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
offset);
return ret_code;
}
/**
* i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
* @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
* @data: word read from the Shadow RAM
*
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
**/
{
DEBUGFUNC("i40e_read_nvm_word_aq");
return ret_code;
}
/**
* i40e_read_nvm_buffer - Reads Shadow RAM buffer
* @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
* @words: (in) number of words to read; (out) number of words actually read
* @data: words read from the Shadow RAM
*
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
* method. The buffer read is preceded by the NVM ownership take
* and followed by the release.
**/
{
#ifdef X722_SUPPORT
#endif
}
/**
* i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
* @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
* @words: (in) number of words to read; (out) number of words actually read
* @data: words read from the Shadow RAM
*
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
* method. The buffer read is preceded by the NVM ownership take
* and followed by the release.
**/
{
DEBUGFUNC("i40e_read_nvm_buffer_srctl");
/* Loop thru the selected region */
if (ret_code != I40E_SUCCESS)
break;
}
/* Update the number of words read from the Shadow RAM */
return ret_code;
}
/**
* i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
* @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
* @words: (in) number of words to read; (out) number of words actually read
* @data: words read from the Shadow RAM
*
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
* method. The buffer read is preceded by the NVM ownership take
* and followed by the release.
**/
{
u16 i = 0;
DEBUGFUNC("i40e_read_nvm_buffer_aq");
do {
/* Calculate number of bytes we should read in this step.
* FVL AQ do not allow to read more than one page at a time or
* to cross page boundaries.
*/
else
/* Check if this is last command, if so set proper flag */
if (ret_code != I40E_SUCCESS)
goto read_nvm_buffer_aq_exit;
/* Increment counter for words already read and move offset to
* new read location
*/
words_read += read_size;
} while (words_read < *words);
for (i = 0; i < *words; i++)
*words = words_read;
return ret_code;
}
/**
* i40e_read_nvm_aq - Read Shadow RAM.
* @hw: pointer to the HW structure.
* @module_pointer: module pointer location in words from the NVM beginning
* @offset: offset in words from module start
* @words: number of words to write
* @data: buffer with words to write to the Shadow RAM
* @last_command: tells the AdminQ that this is the last command
*
* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
**/
bool last_command)
{
DEBUGFUNC("i40e_read_nvm_aq");
/* Here we are checking the SR limit only for the flat memory model.
* We cannot do it for the module-based model, as we did not acquire
* the NVM resource yet (we cannot get the module pointer value).
* Firmware will check the module-based model.
*/
"NVM write error: offset %d beyond Shadow RAM limit %d\n",
else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
/* We can write only up to 4KB (one sector), in one AQ write */
"NVM write fail error: tried to write %d words, limit is %d.\n",
!= (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
/* A single write cannot spread over two sectors */
"NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
else
return ret_code;
}
/**
* i40e_write_nvm_aq - Writes Shadow RAM.
* @hw: pointer to the HW structure.
* @module_pointer: module pointer location in words from the NVM beginning
* @offset: offset in words from module start
* @words: number of words to write
* @data: buffer with words to write to the Shadow RAM
* @last_command: tells the AdminQ that this is the last command
*
* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
**/
bool last_command)
{
DEBUGFUNC("i40e_write_nvm_aq");
/* Here we are checking the SR limit only for the flat memory model.
* We cannot do it for the module-based model, as we did not acquire
* the NVM resource yet (we cannot get the module pointer value).
* Firmware will check the module-based model.
*/
DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
/* We can write only up to 4KB (one sector), in one AQ write */
DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
!= (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
/* A single write cannot spread over two sectors */
DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
else
return ret_code;
}
/**
* i40e_write_nvm_word - Writes Shadow RAM word
* @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to write
* @data: word to write to the Shadow RAM
*
* Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
* NVM ownership have to be acquired and released (on ARQ completion event
* reception) by caller. To commit SR to NVM update checksum function
* should be called.
**/
void *data)
{
DEBUGFUNC("i40e_write_nvm_word");
/* Value 0x00 below means that we treat SR as a flat mem */
}
/**
* i40e_write_nvm_buffer - Writes Shadow RAM buffer
* @hw: pointer to the HW structure
* @module_pointer: module pointer location in words from the NVM beginning
* @offset: offset of the Shadow RAM buffer to write
* @words: number of words to write
* @data: words to write to the Shadow RAM
*
* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
* NVM ownership must be acquired before calling this function and released
* on ARQ completion event reception by caller. To commit SR to NVM update
* checksum function should be called.
**/
{
u32 i = 0;
DEBUGFUNC("i40e_write_nvm_buffer");
for (i = 0; i < words; i++)
/* Here we will only write one buffer as the size of the modules
* mirrored in the Shadow RAM is always less than 4K.
*/
}
/**
* i40e_calc_nvm_checksum - Calculates and returns the checksum
* @hw: pointer to hardware structure
* @checksum: pointer to the checksum
*
* This function calculates SW Checksum that covers the whole 64kB shadow RAM
* except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
* is customer specific and unknown. Therefore, this function skips all maximum
* possible size of VPD (1kB).
**/
{
u16 i = 0;
DEBUGFUNC("i40e_calc_nvm_checksum");
I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
if (ret_code)
/* read pointer to VPD area */
if (ret_code != I40E_SUCCESS) {
}
/* read pointer to PCIe Alt Auto-load module */
if (ret_code != I40E_SUCCESS) {
}
/* Calculate SW checksum that covers the whole 64kB shadow RAM
* except the VPD and PCIe ALT Auto-load modules
*/
/* Read SR page */
if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
if (ret_code != I40E_SUCCESS) {
}
}
/* Skip Checksum word */
if (i == I40E_SR_SW_CHECKSUM_WORD)
continue;
/* Skip VPD module (convert byte size to word count) */
if ((i >= (u32)vpd_module) &&
(i < ((u32)vpd_module +
(I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
continue;
}
/* Skip PCIe ALT module (convert byte size to word count) */
if ((i >= (u32)pcie_alt_module) &&
(i < ((u32)pcie_alt_module +
(I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
continue;
}
}
return ret_code;
}
/**
* i40e_update_nvm_checksum - Updates the NVM checksum
* @hw: pointer to hardware structure
*
* NVM ownership must be acquired before calling this function and released
* on ARQ completion event reception by caller.
* This function will commit SR to NVM.
**/
{
DEBUGFUNC("i40e_update_nvm_checksum");
if (ret_code == I40E_SUCCESS)
return ret_code;
}
/**
* i40e_validate_nvm_checksum - Validate EEPROM checksum
* @hw: pointer to hardware structure
* @checksum: calculated checksum
*
* Performs checksum calculation and validates the NVM SW checksum. If the
* caller does not need checksum, the value can be NULL.
**/
{
DEBUGFUNC("i40e_validate_nvm_checksum");
if (ret_code != I40E_SUCCESS)
/* Do not use i40e_read_nvm_word() because we do not want to take
* the synchronization semaphores twice here.
*/
/* Verify read checksum from EEPROM is the same as
* calculated checksum
*/
if (checksum_local != checksum_sr)
/* If the user cares, return the calculated checksum */
if (checksum)
return ret_code;
}