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/*$FreeBSD: head/sys/dev/ixl/i40e_adminq.c 284049 2015-06-05 22:52:42Z jfv $*/
#include "i40e_status.h"
#include "i40e_type.h"
#include "i40e_register.h"
#include "i40e_adminq.h"
#include "i40e_prototype.h"
/**
* i40e_is_nvm_update_op - return TRUE if this is an NVM update operation
* @desc: API request descriptor
**/
{
}
/**
* i40e_adminq_init_regs - Initialize AdminQ registers
* @hw: pointer to the hardware structure
*
* This assumes the alloc_asq and alloc_arq functions have already been called
**/
{
/* set head and tail registers in our local struct */
if (i40e_is_vf(hw)) {
} else {
}
}
/**
* i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
* @hw: pointer to the hardware structure
**/
{
sizeof(struct i40e_aq_desc)),
if (ret_code)
return ret_code;
sizeof(struct i40e_asq_cmd_details)));
if (ret_code) {
return ret_code;
}
return ret_code;
}
/**
* i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
* @hw: pointer to the hardware structure
**/
{
sizeof(struct i40e_aq_desc)),
return ret_code;
}
/**
* i40e_free_adminq_asq - Free Admin Queue send rings
* @hw: pointer to the hardware structure
*
* This assumes the posted send buffers have already been cleaned
* and de-allocated
**/
{
}
/**
* i40e_free_adminq_arq - Free Admin Queue receive rings
* @hw: pointer to the hardware structure
*
* This assumes the posted receive buffers have already been cleaned
* and de-allocated
**/
{
}
/**
* i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
* @hw: pointer to the hardware structure
**/
{
int i;
/* We'll be allocating the buffer info memory first, then we can
* allocate the mapped buffers for the event processing
*/
/* buffer_info structures do not need alignment */
if (ret_code)
goto alloc_arq_bufs;
/* allocate the mapped buffers */
if (ret_code)
goto unwind_alloc_arq_bufs;
/* now configure the descriptors for use */
/* This is in accordance with Admin queue design, there is no
* register for buffer size configuration
*/
desc->cookie_high = 0;
desc->cookie_low = 0;
}
return ret_code;
/* don't try to free the one that failed... */
i--;
for (; i >= 0; i--)
return ret_code;
}
/**
* i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
* @hw: pointer to the hardware structure
**/
{
int i;
/* No mapped memory needed yet, just the buffer info structures */
if (ret_code)
goto alloc_asq_bufs;
/* allocate the mapped buffers */
if (ret_code)
goto unwind_alloc_asq_bufs;
}
return ret_code;
/* don't try to free the one that failed... */
i--;
for (; i >= 0; i--)
return ret_code;
}
/**
* i40e_free_arq_bufs - Free receive queue buffer info elements
* @hw: pointer to the hardware structure
**/
{
int i;
/* free descriptors */
/* free the descriptor memory */
/* free the dma header */
}
/**
* i40e_free_asq_bufs - Free send queue buffer info elements
* @hw: pointer to the hardware structure
**/
{
int i;
/* only unmap if the address is non-NULL */
/* free the buffer info list */
/* free the descriptor memory */
/* free the dma header */
}
/**
* i40e_config_asq_regs - configure ASQ registers
* @hw: pointer to the hardware structure
*
* Configure base address and length registers for the transmit queue
**/
{
/* Clear Head and Tail */
/* set starting point */
if (!i40e_is_vf(hw))
if (i40e_is_vf(hw))
/* Check one register to verify that config was applied */
return ret_code;
}
/**
* i40e_config_arq_regs - ARQ register configuration
* @hw: pointer to the hardware structure
*
* Configure base address and length registers for the receive (event queue)
**/
{
/* Clear Head and Tail */
/* set starting point */
if (!i40e_is_vf(hw))
if (i40e_is_vf(hw))
/* Update tail in the HW to post pre-allocated buffers */
/* Check one register to verify that config was applied */
return ret_code;
}
/**
* i40e_init_asq - main initialization routine for ASQ
* @hw: pointer to the hardware structure
*
* This is the main initialization routine for the Admin Send Queue
* Prior to calling this function, drivers *MUST* set the following fields
* in the hw->aq structure:
* - hw->aq.num_asq_entries
* - hw->aq.arq_buf_size
*
* Do *NOT* hold the lock when calling this as the memory allocation routines
* called are not going to be atomic context safe
**/
{
/* queue already initialized */
goto init_adminq_exit;
}
/* verify input for valid configuration */
goto init_adminq_exit;
}
/* allocate the ring memory */
if (ret_code != I40E_SUCCESS)
goto init_adminq_exit;
/* allocate buffers in the rings */
if (ret_code != I40E_SUCCESS)
goto init_adminq_free_rings;
/* initialize base registers */
if (ret_code != I40E_SUCCESS)
goto init_adminq_free_rings;
/* success! */
goto init_adminq_exit;
return ret_code;
}
/**
* i40e_init_arq - initialize ARQ
* @hw: pointer to the hardware structure
*
* The main initialization routine for the Admin Receive (Event) Queue.
* Prior to calling this function, drivers *MUST* set the following fields
* in the hw->aq structure:
* - hw->aq.num_asq_entries
* - hw->aq.arq_buf_size
*
* Do *NOT* hold the lock when calling this as the memory allocation routines
* called are not going to be atomic context safe
**/
{
/* queue already initialized */
goto init_adminq_exit;
}
/* verify input for valid configuration */
goto init_adminq_exit;
}
/* allocate the ring memory */
if (ret_code != I40E_SUCCESS)
goto init_adminq_exit;
/* allocate buffers in the rings */
if (ret_code != I40E_SUCCESS)
goto init_adminq_free_rings;
/* initialize base registers */
if (ret_code != I40E_SUCCESS)
goto init_adminq_free_rings;
/* success! */
goto init_adminq_exit;
return ret_code;
}
/**
* i40e_shutdown_asq - shutdown the ASQ
* @hw: pointer to the hardware structure
*
* The main shutdown routine for the Admin Send Queue
**/
{
return I40E_ERR_NOT_READY;
/* Stop firmware AdminQ processing */
/* make sure spinlock is available */
/* free ring buffers */
return ret_code;
}
/**
* i40e_shutdown_arq - shutdown ARQ
* @hw: pointer to the hardware structure
*
* The main shutdown routine for the Admin Receive Queue
**/
{
return I40E_ERR_NOT_READY;
/* Stop firmware AdminQ processing */
/* make sure spinlock is available */
/* free ring buffers */
return ret_code;
}
/**
* i40e_init_adminq - main initialization routine for Admin Queue
* @hw: pointer to the hardware structure
*
* Prior to calling this function, drivers *MUST* set the following fields
* in the hw->aq structure:
* - hw->aq.num_asq_entries
* - hw->aq.num_arq_entries
* - hw->aq.arq_buf_size
* - hw->aq.asq_buf_size
**/
{
int retry = 0;
/* verify input for valid configuration */
goto init_adminq_exit;
}
/* initialize spin locks */
/* Set up register offsets */
/* setup ASQ command write back timeout */
/* allocate the ASQ */
if (ret_code != I40E_SUCCESS)
/* allocate the ARQ */
if (ret_code != I40E_SUCCESS)
goto init_adminq_free_asq;
/* VF has no need of firmware */
if (i40e_is_vf(hw))
goto init_adminq_exit;
/* There are some cases where the firmware may not be quite ready
* for AdminQ operations, so we retry the AdminQ setup a few times
* if we see timeouts in this first AQ call.
*/
do {
NULL);
if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
break;
retry++;
i40e_msec_delay(100);
} while (retry < 10);
if (ret_code != I40E_SUCCESS)
goto init_adminq_free_arq;
/* get the NVM version info */
&oem_hi);
&oem_lo);
goto init_adminq_free_arq;
}
/* pre-emptive resource lock release */
0,
NULL);
/* success! */
goto init_adminq_exit;
return ret_code;
}
/**
* i40e_shutdown_adminq - shutdown routine for the Admin Queue
* @hw: pointer to the hardware structure
**/
{
if (i40e_check_asq_alive(hw))
/* destroy the spinlocks */
return ret_code;
}
/**
* i40e_clean_asq - cleans Admin send queue
* @hw: pointer to the hardware structure
*
* returns the number of free desc
**/
{
}
ntc++;
ntc = 0;
}
return I40E_DESC_UNUSED(asq);
}
/**
* i40e_asq_done - check if FW has processed the Admin Send Queue
* @hw: pointer to the hw struct
*
* Returns TRUE if the firmware has processed all descriptors on the
* admin send queue. Returns FALSE if there are still requests pending.
**/
{
/* AQ designers suggest use of head for better
* timing reliability than DD bit
*/
}
/**
* i40e_asq_send_command - send command to Admin Queue
* @hw: pointer to the hw struct
* @desc: prefilled descriptor describing the command (non DMA mem)
* @buff: buffer to use for indirect commands
* @buff_size: size of buffer for indirect commands
* @cmd_details: pointer to command details structure
*
* This is the main send command driver routine for the Admin Queue send
* queue. It runs the queue, cleans the queue, etc
**/
struct i40e_aq_desc *desc,
void *buff, /* can be NULL */
struct i40e_asq_cmd_details *cmd_details)
{
"AQTX: head overrun at %d\n", val);
goto asq_send_command_exit;
}
"AQTX: Admin queue not initialized.\n");
goto asq_send_command_exit;
}
if (cmd_details) {
sizeof(struct i40e_asq_cmd_details),
/* If the cmd_details are defined copy the cookie. The
* CPU_TO_LE32 is not needed here because the data is ignored
* by the FW, only used by the driver
*/
desc->cookie_high =
desc->cookie_low =
}
} else {
i40e_memset(details, 0,
sizeof(struct i40e_asq_cmd_details),
}
/* clear requested flags and then set additional flags if defined */
"AQTX: Invalid buffer size: %d.\n",
goto asq_send_command_error;
}
"AQTX: Async flag not set along with postpone flag");
goto asq_send_command_error;
}
/* call clean and check queue available function to reclaim the
* descriptors that were processed by FW, the function returns the
* number of desc available
*/
/* the clean function called here could be called in a separate thread
* in case of asynchronous completions
*/
if (i40e_clean_asq(hw) == 0) {
"AQTX: Error queue is full.\n");
goto asq_send_command_error;
}
/* initialize the temp desc pointer with the right desc */
/* if the desc is available copy the temp desc to the right place */
/* if buff is not NULL assume indirect command */
/* copy the user buff into the respective DMA buff */
/* Update the address values in the desc with the pa value
* for respective buffer
*/
}
/* bump the tail */
/* if cmd_details are not defined or async flag is not set,
* we need to wait for desc write back
*/
do {
/* AQ designers suggest use of head for better
* timing reliability than DD bit
*/
if (i40e_asq_done(hw))
break;
/* ugh! delay while spin_lock */
i40e_msec_delay(1);
total_delay++;
}
/* if ready, copy the desc back to temp */
if (i40e_asq_done(hw)) {
if (retval != 0) {
"AQTX: Command completed with error 0x%X.\n",
retval);
/* strip off FW internal code */
retval &= 0xff;
}
else
}
"AQTX: desc and buffer writeback:\n");
/* save writeback aq if requested */
sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA);
/* update the error if time out occurred */
if ((!cmd_completed) &&
"AQTX: Writeback timeout.\n");
}
return status;
}
/**
* i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
* @desc: pointer to the temp descriptor (non DMA mem)
* @opcode: the opcode can be used to decide which flags to turn off or on
*
* Fill the desc with default values
**/
{
/* zero out the desc */
}
/**
* i40e_clean_arq_element
* @hw: pointer to the hw struct
* @e: event info from the receive descriptor, includes any buffers
* @pending: number of events that could be left to process
*
* This function cleans one Admin Receive Queue element and returns
* the contents through e. It can also return how many events are
* left to process through 'pending'
**/
struct i40e_arq_event_info *e,
{
/* take the lock before we start messing with the ring */
/* set next_to_use to head */
if (!i40e_is_vf(hw))
if (i40e_is_vf(hw))
/* nothing to do - shouldn't need to update ring's values */
goto clean_arq_element_out;
}
/* now clean the next descriptor */
if (flags & I40E_AQ_FLAG_ERR) {
"AQRX: Event received with error 0x%X.\n",
}
i40e_memcpy(e->msg_buf,
e->msg_len, I40E_DMA_TO_NONDMA);
/* Restore the original datalen and buffer address in the desc,
* FW updates datalen to indicate the event message
* size
*/
/* set tail = the last cleaned desc index. */
/* ntc is updated to tail + 1 */
ntc++;
ntc = 0;
/* Set pending if needed, unlock and return */
if (i40e_is_nvm_update_op(&e->desc)) {
}
switch (hw->nvmupd_state) {
break;
break;
default:
break;
}
}
return ret_code;
}
{
/* Registers are reset after PF reset */
}