/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _HXGE_PEU_HW_H
#define _HXGE_PEU_HW_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Register: DeviceVendorId
* Device ID and Vendor ID
* Fields:
* Device ID Register: dbi writeable
* Vendor ID Register (Sun Microsystem): dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: StatusCommand
* Status and Command
* Fields:
* The device detected a parity error. The device detects
* Poisoned TLP received regardless of Command Register Parity
* The device signaled a system error with SERR#. The device
* the Command Register SERR# enable is set.
* A transaction initiated by this device was terminated due to a
* Master Abort (i.e. Unsupported Request Completion Status was
* received).
* A transaction initiated by this device was terminated due to a
* Target Abort (i.e. Completer Abort Completion Status was
* received).
* Set when Completer Abort Completion Status is sent back to the
* RC. The request violated hydra's programming rules.
* The slowest DEVSEL# timing for this target device (N/A in
* PCIE)
* Master Data Parity Error - set if all the following conditions
* are true: received a poisoned TLP header or sending a poisoned
* write request; and the parity error response bit in the
* command register is set.
* Fast Back-to-Back Capable (N/A in PCIE)
* 66 MHz Capable (N/A in PCIE)
* Capabilities List - presence of extended capability item.
* INTx Status
* INTx Assertion Disable
* Fast Back-to-Back Enable (N/A in PCIE)
* This device can drive the SERR# line.
* This device can drive the PERR# line.
* VGA Palette Snoop (N/A in PCIE)
* The device can issue Memory Write-and-Invalidate commands (N/A
* in PCIE)
* This device monitors for PCI Special Cycles (N/A in PCIE)
* This device's bus master capability is enabled.
* This device responds to PCI memory accesses.
* This device responds to PCI IO accesses (No I/O space used in
* Hydra)
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: ClasscodeRevId
* Class Code, and Revision ID
* Fields:
* Base Class (Network Controller): dbi writeable
* Sub Class (Ethernet Controller): dbi writeable
* Programming Interface: dbi writeable
* Revision ID: dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: BistHdrtypLattmrCashlsz
* BIST, Header Type, Latency Timer, and Cache Line Size
* Description: BIST, Latency Timer etc
* Fields:
* BIST is not supported. Header Type Fields
* Multi-Function Device: dbi writeable
* Configuration Header Format. 0 = Type 0.
* Master Latency Timer. (N/A in PCIE)
* Cache line size for legacy compatibility (N/A in PCIE)
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PioBar0
* PIO BAR0
* Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0
* are together configured as a 64b BAR register (Synopsys core
* implementation dependent) where PIO BAR1 handles the upper address
* bits and PIO BAR0 handles the lower address bits.
* Fields:
* Base Address Relocation : indirect dbi writeable via bar0Mask
* register in EP core
* Base Address for PIO (16MB space) : indirect dbi writeable via
* bar0Mask register in EP core
* Prefetchable if memory BAR (PIOs not prefetchable): dbi
* writeable
* If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64
* bit): dbi writeable
* I/O or Memory space indicator (0 = memory BAR): dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} pio_bar0_t;
/*
* Register: PioBar1
* PIO BAR1
* Description: PIO BAR1
* Fields:
* Base Address Relocation : indirect dbi writeable via bar0Mask
* register in EP core
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} pio_bar1_t;
/*
* Register: MsixBar0
* MSIX BAR0
* Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX
* BAR0 are together configured as a 64b BAR register (Synopsys core
* implementation dependent) where MSIX BAR1 handles the upper
* address bits and MSIX BAR0 handles the lower address bits.
* Fields:
* Base Address Relocation : indirect dbi writeable via bar2Mask
* register in EP core
* Base Address for MSIX (16KB space) : indirect dbi writeable
* via bar2Mask register in EP core
* Prefetchable if memory BAR (Not prefetchable) : dbi writeable
* If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64
* bit): dbi writeable
* I/O or Memory space indicator (0 = memory BAR) : dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} msix_bar0_t;
/*
* Register: MsixBar1
* MSIX BAR1
* Description: MSIX BAR1
* Fields:
* Base Address Relocation : indirect dbi writeable via bar2Mask
* register in EP core
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} msix_bar1_t;
/*
* Register: VirtBar0
* Virtualization BAR0
* Description: Virtualization BAR0 - Previously for Hydra
* Virtualization space This bar is no longer enabled and is not dbi
* writeable. VIRT BAR1 & VIRT BAR0 could be configured as a 64b BAR
* register (Synopsys core implementation dependent), but this is not
* used in hydra.
* Fields:
* Base Address Relocation
* Base Address for Virtualization (64KB space)
* Prefetchable if memory BAR (Not prefetchable)
* If memory BAR, then 32 or 64 bit BAR (00 = 32 bit, 10 = 64
* bit)
* I/O or Memory space indicator (0 = memory BAR)
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} virt_bar0_t;
/*
* Register: VirtBar1
* Virtualization BAR1
* Description: Previously for Virtualization BAR1 This bar is no
* longer enabled and is not dbi writeable.
* Fields:
* Base Address Relocation
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} virt_bar1_t;
/*
* Register: CisPtr
* CardBus CIS Pointer
* Description: CardBus CIS Pointer
* Fields:
* CardBus CIS Pointer: dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} cis_ptr_t;
/*
* Register: SubVendorId
* Subsystem ID and Vendor ID
* Description: Subsystem ID and Vendor ID
* Fields:
* Subsystem ID as assigned by PCI-SIG : dbi writeable
* Subsystem Vendor ID as assigned by PCI-SIG : dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: ExpRomBar
* Expansion ROM BAR
* Description: Expansion ROM BAR - For Hydra EEPROM space
* Fields:
* Base Address Relocatable : indirect dbi writeable via
* romBarMask register in EP core
* Base Address for ROM (2MB) : indirect dbi writeable via
* romBarMask register in EP core
* ROM Enable: dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CapPtr
* Capabilities Pointer
* Description: Capabilities Pointer
* Fields:
* Pointer to PM Capability structure : dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} cap_ptr_t;
/*
* Register: IntLine
* Interrupt Line
* Description: Interrupt Line
* Fields:
* Max Latency (N/A in PCIE)
* Minimum Grant (N/A in PCIE)
* Interrupt pin: dbi writeable
* Interrupt Line
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} int_line_t;
/*
* Register: PmCap
* Power Management Capability
* Description: Power Management Capability
* Fields:
* PME Support (N/A in Hydra): dbi writeable
* D2 Support (N/A in Hydra): dbi writeable
* D1 Support (N/A in Hydra): dbi writeable
* Aux Current (N/A in Hydra): dbi writeable
* Device Specific Initialization: dbi writeable
* PME Clock (N/A in PCIE)
* PM Spec Version: dbi writeable
* Next Capability Pointer: dbi writeable
* Power Management Capability ID: dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} pm_cap_t;
/*
* Register: PmCtrlStat
* Power Management Control and Status
* Description: Power Management Control and Status
* Fields:
* Data for additional info (N/A)
* Bus Power and Clock Control Enable (N/A in PCIE)
* Indicates if PME event occured
* Data Scale (N/A)
* Data Select (N/A)
* PME Enable (Sticky)
* Power State
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: MsiCap
* MSI Capability
* Description: MSI Capability
* Fields:
* Mask and Pending bits available
* 64-bit Address Capable
* Multiple Messages Enabled
* Multiple Message Capable (32 messages = 0x5)
* MSI Enabled (if enabled, INTx must be diabled)
* Next Capability Pointer: dbi writeable
* MSI Capability ID
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} msi_cap_t;
/*
* Register: MsiLoAddr
* MSI Low Address
* Description: MSI Low Address
* Fields:
* Lower 32 bit Address
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: MsiHiAddr
* MSI High Address
* Description: MSI High Address
* Fields:
* Upper 32 bit Address (only if msi64En = 1)
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: MsiData
* MSI Data
* Description: MSI Data
* Fields:
* MSI Data. Depending on the value for multMsgEn in the MSI
* Capability Register which determines the number of allocated
* vectors, bits [4:0] may be replaced with msiVector[4:0] bits
* to generate up to 32 MSI messages. # allocated vectors Actual
* messageData[4:0] ------------------- ------------------------
* 1 DATA[4:0] (no replacement) 2 {DATA[4:1], msiVector[0]} 4
* {DATA[4:2], msiVector[1:0]} 8 {DATA[4:3], msiVector[2:0]} 16
* {DATA[4], msiVector[3:0]} 32 msiVector[4:0] (full replacement)
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} msi_data_t;
/*
* Register: MsiMask
* MSI Mask
* Description: MSI Mask
* Fields:
* per vector MSI Mask bits
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} msi_mask_t;
/*
* Register: MsiPend
* MSI Pending
* Description: MSI Pending
* Fields:
* per vector MSI Pending bits
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} msi_pend_t;
/*
* Register: MsixCap
* MSIX Capability
* Description: MSIX Capability
* Fields:
* MSIX Enable (if enabled, MSI and INTx must be disabled)
* Function Mask (1 = all vectors masked regardless of per vector
* mask, 0 = each vector's mask
* Table Size (0x1F = 32 entries): dbi writeable
* Next Capability Pointer: dbi writeable
* MSIX Capability ID
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} msix_cap_t;
/*
* Register: MsixTabOff
* MSIX Table Offset
* Description: MSIX Table Offset
* Fields:
* Table Offset (Base address of MSIX Table = msixTabBir.BAR +
* msixTabOff) : dbi writeable
* Table BAR Indicator (0x2 = BAR2 at loc 0x18) : dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: MsixPbaOff
* MSIX PBA Offset
* Description: MSIX PBA Offset
* Fields:
* Pending Bit Array (PBA) Offset (Base address of MSIX Table =
* msixTabBir.BAR + msixPbaOff); msixPbaOff is quad-aligned, i.e.
* starts at 0x2000 (half-way in MSI-X bar space. : dbi writeable
* Pending Bit Array (PBA) BAR Indicator (0x2 = BAR2 at loc 0x18)
* : dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PcieCap
* PCIE Capability
* Description: PCIE Capability
* Fields:
* Interrupt Message Number (updated by HW)
* Slot Implemented (Endpoint must be 0)
* PCIE Express Device Port Type (Endpoint)
* PCIE Express Capability Version
* Next Capability Pointer: dbi writeable
* PCI Express Capability ID
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} pcie_cap_t;
/*
* Register: DevCap
* Device Capability
* Description: Device Capability
* Fields:
* Slot Power Limit Scale (Msg from RC) Hydra can capture
* Received setSlotPowerLimit message; values in this field are
* ignored as no power scaling is possible.
* Slot Power Limit Value (Msg from RC) Hydra can capture
* Received setSlotPowerLimit message; values in this field are
* ignored as no power scaling is possible.
* Introduced in PCIe 1.1 specification. : dbi writeable
* L1 Acceptable Latency (4 - 8 us) : dbi writeable
* LOs Acceptable Latency (2 - 4 us) : dbi writeable
* Extended Tag Field Support (N/A) : dbi writeable
* Phantom Function Supported (N/A) : dbi writeable
* Maximum Payload Size supported (Hydra = 1KB) : dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} dev_cap_t;
/*
* Register: DevStatCtrl
* Device Status and Control
* Description: Device Control
* Fields:
* Transaction Pending (1 if NP request not completed)
* Auxilliary Power Detected (1 if detected)
* Unsupported Request Detect
* Fatal Error Detected
* Non-Fatal Error Detected
* Correctable Error Detected ----- Control Fields
* Introduced in PCIe 1.1 specification.
* Maximum Read Request Size (default = 512B) for the device as a
* requester. 3'b000: 128 Bytes 3'b001: 256 Bytes 3'b010: 512
* Bytes 3'b011: 1K Bytes 3'b100: 2K Bytes 3'b101: 4K Bytes
* 3'b110: Reserved 3'b111: Reserved
* No Snoop Enable This bit indicates the device "could", not
* that it does. Both this bit and the hydra specific peuCip
* register bit must be set for the value of this bit to impact
* the TLP header no snoop attribute. When both are set, hydra
* sets the no snoop attribute on all initiated TLPs. Software
* must guarantee the No Snoop attribute is used in the system
* correctly.
* Auxilliary Power PM Enable
* Phantom Function enable
* Extended Tag Field Enable
* Maximum Payload Size. 3-bit value has the same encodings as
* the maxRdSz field.
* Relaxed Ordering Enable This bit indicates the device "could",
* not that it does. Both this bit and the hydra specific peuCip
* register bit must be set for the value of this bit to impact
* the TLP header relaxed ordering attribute. When both are set,
* packet operations set the relaxed ordering attribute. Mailbox
* updates always set the relaxed ordering attribute to 0,
* regardless of this bit. When this bit is 0, the default
* Unsupported Request Report Enable
* Fatal Error Report Enable
* Non-Fatal Error Report Enable
* Correctable Error Report Enable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: LnkCap
* Link Capability
* Description: Link Capability
* Fields:
* Port Number : dbi writeable
* Introduced in PCIe 1.1 specification.
* Introduced in PCIe 1.1 specification.
* Default Clock Power Management (N/A) Introduced in PCIe 1.1
* specification. : dbi writeable
* Default L1 Exit Latency (32us to 64us => 0x6) : dbi writeable
* Default L0s Exit Latency (1us to 2us => 0x5) : dbi writeable
* Active Link PM Support (only L0s = 1) : dbi writeable
* Maximum Link Width (x8) : dbi writeable
* Maximum Link Speed (2.5 Gbps = 1) : dbi writeable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} lnk_cap_t;
/*
* Register: LnkStatCtrl
* Link Status and Control
* Description: Link Control
* Fields:
* Slot Clock Configuration (0 = using independent clock; pg 266
* PCIe 1.1) : dbi writeable
* Link Training (N/A for EP)
* Training Error (N/A for EP)
* Negotiated Link Width (Max negotiated: x8)
* Negotiated Link Speed (Max negotiated: 1 = 2.5 Gbps) -----
* Control Fields
* Introduced in PCIe 1.1.
* Extended Synch
* Common Clock Configuration
* Retrain Link (N/A for EP)
* Link Disable (N/A for EP)
* Read Completion Boundary (128B)
* Active State Link PM Control
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: VenCapHdr
* Vendor Specific Capability Header
* Description: Vendor Specific Capability Header
* Fields:
* Length
* Next Capbility Pointer
* Vendor Specific Capbility ID
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: VenCtrl
* Vendor Specific Control
* Description: Vendor Specific Control
* Fields:
* PCIe spec absolute minimum is 50usec - (likely ~10ms). PCIe
* spec absolute max is 50msec. Default set for 22.2 msec via
* adding time as follows: Bit 23: 3.21 secs <---POR 0 Bit 22:
* 201.3 msec <---POR 0 Bit 21: 100.8 msec <---POR 0 Bit 20: 25.2
* msec <---POR 0 Bit 19: 12.6 msec <---POR 1 Bit 18: 6.3 msec
* <---POR 1 Bit 17: 3.3 msec <---POR 1 Bit 16: if 0:
* Baseline0=50usec; else Baseline1(use for
* simulation-only)=804nsec
* Interrupt Control Mode (00 = Reserved, 01 = INTx emulation, 10
* = Reserved [Neptune INTx pins], 11 = Reserved [Neptune INTx
* emulation + pins]
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} ven_ctrl_t;
/*
* Register: VenPrtHdr
* Vendor Specific Port Logic Header
* Description: Vendor Specific Port Logic Header
* Fields:
* Length
* Next Capbility Pointer (END, no more)
* Vendor Specific Capbility ID
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: AcklatReplay
* Ack Latency and Replay Timer register
* Fields:
* Replay Time limit = 16'd12429/`cxNb where cxNb=1.
* Round Trip Latency Time limit = 9d'4143/`cxNb where cxNb=1.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: OthMsg
* Other Message Register
* Description: Other Message Register
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} oth_msg_t;
/*
* Register: ForceLink
* Port Force Link
* Description: Other Message Register
* Fields:
* LinkState that the EP core will be forced to when ForceLink
* (bit[15]) is set
* Forces Link to the specified LinkState field below. Write this
* bit to generate a pulse to the ltssm. It clears itself once
* the pulse is generated. Read will always return 0.
* Link Number - N/A for Endpoint
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} force_link_t;
/*
* Register: AckFreq
* ACK Frequency Register
* Description: ACK Frequency Register
* Fields:
* NFTS = 115.
* NFTS = 115.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} ack_freq_t;
/*
* Register: LinkCtrl
* Port Link Control
* Description: Port Link Control
* Fields:
* 8 lanes
* When set, this bit is only set for 1 cycle. A write of 0 has
* no effect.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} link_ctrl_t;
/*
* Register: LaneSkew
* Lane Skew Register
* Description: Lane Skew Register
* Fields:
* prevents EP core from sending FC DLLPs
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} lane_skew_t;
/*
* Register: SymbolNum
* Symbol Number Register
* Description: Symbol Number Register
* Fields:
* Timer modifier for Flow control Watch Dog timer
* Timer modifier for Replay timer
* Note: rtl uses defaultNSkipSymbols
* Note: rtl initialized using defaultNTs1Symbols
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} symbol_num_t;
/*
* Register: SymbTimRadmFlt1
* Symbol Timer Register / RADM Filter Mask Register 1
* Description: Symbol Timer / RADM Filter Mask 1
* Fields:
* No masking errors while filtering
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: RadmFlt2
* RADM Filter Mask Register 2
* Description: RADM Filter Mask Register 2
* Fields:
* [31:2] = Reserved [1]=0=Vendor MSG Type0 dropped & treated as
* UR, [0]=0=Vendor MSG Type1 silently dropped.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} radm_flt2_t;
/*
* Register: CascadeDebReg0
* Cascade core (EP) Debug Register 0
* Description: Debug Register 0 EP Core SII Interface bus :
* cxplDebugInfo[31:0]
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CascadeDebReg1
* Cascade Core (EP) Debug Register 1
* Description: Debug Register 1 EP Core SII Interface bus :
* cxplDebugInfo[63:32]
* Fields:
* PCIe Link status. 0=down, 1=up
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: TxpFcCreditStat
* Transmit Posted FC Credit Status
* Description: Transmit Posted FC Credit Status
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: TxnpFcCreditStat
* Transmit Non-Posted FC Credit Status
* Description: Transmit Non-Posted FC Credit Status
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: TxcplFcCreditStat
* Transmit Completion FC Credit Status
* Description: Transmit Completion FC Credit Status
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: QueueStat
* Queue Status
* Description: Queue Status
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} queue_stat_t;
/*
* Register: GbtDebug0
* GBT Debug, Status register
* Description: This register returns bits [31:0] of the PIPE core's
* gbtDebug bus
* Fields:
* [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
* tbcout10O will always read 1'b0
* The value specified here is the Power On Reset value as given
* in spec. except for the clock bits which are hardwired to
* 1'b0.
* The gbtDebug[0:15] bus is provided for each lane as an output
* from the pcieGbtopWrapper.v module. These signals are not
* required for manufacturing test and may be left unconnected.
* The cw00041130PipeParam.vh bus width is the number of lanes
* multiplied by 16. lane0 is bits[15:0], lane1 is bits[31:16],
* lane2 is bits[47:32], lane3 is bits[63:48], lane4 is
* bits[79:64], lane5 is bits[95:80], lane6 is bits[111:96],
* lane7 is bits[127:112].
* Refer to section 4.2.2.4, Gigablaze Debug Signals section.
* (pgs 4.27 - 4.28) in the following document :
* cw000411TechMan.pdf
* lane0 is bits[15:0], which is gbtDebug0[15:0] lane1 is
* bits[31:16], which is gbtDebug0[31:16]
*
* -------------------------------------------------------------------------
* Signal Bit Reset Description
* -------------------------------------------------------------------------
* gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
* gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
* gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
* [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
* [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
* 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
* [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
* [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
* loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
* active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
* 0 reserved
* -------------------------------------------------------------------------
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} gbt_debug0_t;
/*
* Register: GbtDebug1
* GBT Debug, Status register
* Description: This register returns bits [63:32] of the PIPE core's
* gbtDebug bus
* Fields:
* [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
* tbcout10O will always read 1'b0
* The value specified here is the Power On Reset value as given
* in spec. except for the clock bits which are hardwired to
* 1'b0.
* The gbtDebug[0:15] bus is provided for each lane as an output
* from the pcieGbtopWrapper.v module. These signals are not
* required for manufacturing test and may be left unconnected.
* The cw00041130PipeParam.vh bus width is the number of lanes
* multiplied by 16.
* Refer to section 4.2.2.4, Gigablaze Debug Signals section.
* (pgs 4.27 - 4.28) in the following document :
* cw000411TechMan.pdf
* lane2 is bits[47:32], which is gbtDebug1[15:0] lane3 is
* bits[63:48], which is gbtDebug1[31:16]
*
* -------------------------------------------------------------------------
* Signal Bit Reset Description
* -------------------------------------------------------------------------
* gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
* gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
* gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
* [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
* [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
* 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
* [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
* [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
* loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
* active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
* 0 reserved
* -------------------------------------------------------------------------
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} gbt_debug1_t;
/*
* Register: GbtDebug2
* GBT Debug, Status register
* Description: This register returns bits [95:64] of the PIPE core's
* gbtDebug bus
* Fields:
* [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
* tbcout10O will always read 1'b0
* The value specified here is the Power On Reset value as given
* in spec. except for the clock bits which are hardwired to
* 1'b0.
* The gbtDebug[0:15] bus is provided for each lane as an output
* from the pcieGbtopWrapper.v module. These signals are not
* required for manufacturing test and may be left unconnected.
* The cw00041130PipeParam.vh bus width is the number of lanes
* multiplied by 16.
* Refer to section 4.2.2.4, Gigablaze Debug Signals section.
* (pgs 4.27 - 4.28) in the following document :
* cw000411TechMan.pdf
* lane4 is bits[79:64], which is gbtDebug2[15:0] lane5 is
* bits[95:80], which is gbtDebug2[31:16]
*
* -------------------------------------------------------------------------
* Signal Bit Reset Description
* -------------------------------------------------------------------------
* gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
* gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
* gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
* [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
* [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
* 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
* [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
* [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
* loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
* active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
* 0 reserved
* -------------------------------------------------------------------------
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} gbt_debug2_t;
/*
* Register: GbtDebug3
* GBT Debug, Status register
* Description: This register returns bits [127:96] of the PIPE
* core's gbtDebug bus
* Fields:
* [6] & [22] = rxclkO will always read 1'b0 [7] & [23] =
* tbcout10O will always read 1'b0
* The value specified here is the Power On Reset value as given
* in spec. except for the clock bits which are hardwired to
* 1'b0.
* The gbtDebug[0:15] bus is provided for each lane as an output
* from the pcieGbtopWrapper.v module. These signals are not
* required for manufacturing test and may be left unconnected.
* The cw00041130PipeParam.vh bus width is the number of lanes
* multiplied by 16.
* Refer to section 4.2.2.4, Gigablaze Debug Signals section.
* (pgs 4.27 - 4.28) in the following document :
* cw000411TechMan.pdf
* lane6 is bits[111:96], which is gbtDebug3[15:0] lane7 is
* bits[127:112], which is gbtDebug3[31:16]
*
* -------------------------------------------------------------------------
* Signal Bit Reset Description
* -------------------------------------------------------------------------
* gbtResetRbcI [16n+15] [15] 1 Reset receiver bit clock
* gbtResetTbc20I [16n+14] [14] 1 Reset transmit 20-bit clock
* gbtResetRI [16n+13] [13] 1 Reset receiver logic gbtResetTI
* [16n+12] [12] 1 Reset transmit logic reserved [16n+11:16n+8]
* [11:8] 0 reserved gbtTbcout10 [16n+7] [7] 1 transmit clock
* 10-bit gbtRxclkO [16n+6] [6] 0 receiver PLL clock gbtRxpresO
* [16n+5] [5] 0 receiver detect present gbtRxpresvalidO [16n+4]
* [4] 0 gbtRxpresO is valid gbtRxlosO [16n+3] [3] 1 raw receiver
* loss-of-signal gbtPassnO [16n+2] [2] 1 GigaBlaze BIST pass
* active low reserved [16n+1] [1] 0 reserved reserved [16n] [0]
* 0 reserved
* -------------------------------------------------------------------------
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} gbt_debug3_t;
/*
* Register: PipeDebug0
* PIPE Debug, status register
* Description: This register returns bits [31:0] of the PIPE core's
* gbtDebug bus
* Fields:
* The value specified here is the Power On Reset value as given
* in spec.
* This 16-bit debug bus reports operating conditions for the
* PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
* is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
* lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
* bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
* Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
* the following document :
* cw000411TechMan.pdf
* lane0 is bit[15:0], which is pipeDebug0[15:0] lane1 is
* bit[31:16], which is pipeDebug0[31:16]
*
* -------------------------------------------------------------------------
* pipeDebug Signal or Condition Description Reset
* -------------------------------------------------------------------------
* [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
* underflow occurred
* [14] skipInsert or EFIFO skip inserted or 0 skipDelete
* deleted 0
* [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
* Used with skipcharflag to verify EFIFO depth.
* [12] skipcharflag Skip flag written by EFIFO 0
* [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
* [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
* output
* [6] efifoBytesync EFIFO output byte 0 synchronization
* [5] rxinvalid 8b/10b error or 0 or code violation
* [4] rxinitdone Receiver bit-init done. 0 Synchronous with
* pipeClk.
* [3] txinitdone Transmitter-bit init done. 0 Synchronous with
* pipeClk.
* [2] filteredrxlos Filtered loss of signal used 1 to generate
* p2lRxelectidle. Synchronous with pipeClk.
* [1] rxdetectInt Receiver detected 0
* [0] pipeMasterDoneOut Receiver detection valid 0
*
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeDebug1
* PIPE Debug, status register
* Description: This register returns bits [63:32] of the PIPE core's
* gbtDebug bus
* Fields:
* The value specified here is the Power On Reset value as given
* in spec.
* This 16-bit debug bus reports operating conditions for the
* PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
* is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
* lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
* bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
* Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
* the following document :
* cw000411TechMan.pdf
* lane2 is bits[47:32], which is pipeDebug1[15:0] lane3 is
* bits[63:48], which is pipeDebug1[31:16]
*
* -------------------------------------------------------------------------
* pipeDebug Signal or Condition Description Reset
* -------------------------------------------------------------------------
* [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
* underflow occurred
* [14] skipInsert or EFIFO skip inserted or 0 skipDelete
* deleted 0
* [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
* Used with skipcharflag to verify EFIFO depth.
* [12] skipcharflag Skip flag written by EFIFO 0
* [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
* [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
* output
* [6] efifoBytesync EFIFO output byte 0 synchronization
* [5] rxinvalid 8b/10b error or 0 or code violation
* [4] rxinitdone Receiver bit-init done. 0 Synchronous with
* pipeClk.
* [3] txinitdone Transmitter-bit init done. 0 Synchronous with
* pipeClk.
* [2] filteredrxlos Filtered loss of signal used 1 to generate
* p2lRxelectidle. Synchronous with pipeClk.
* [1] rxdetectInt Receiver detected 0
* [0] pipeMasterDoneOut Receiver detection valid 0
*
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeDebug2
* PIPE Debug, status register
* The value specified here is the Power On Reset value as given
* in spec.
* This 16-bit debug bus reports operating conditions for the
* PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
* is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
* lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
* bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
* Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
* the following document :
* cw000411TechMan.pdf
* lane4 is bits[79:64], which is pipeDebug2[15:0] lane5 is
* bits[95:80], which is pipeDebug2[31:16]
*
* -------------------------------------------------------------------------
* pipeDebug Signal or Condition Description Reset
* -------------------------------------------------------------------------
* [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
* underflow occurred
* [14] skipInsert or EFIFO skip inserted or 0 skipDelete
* deleted 0
* [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
* Used with skipcharflag to verify EFIFO depth.
* [12] skipcharflag Skip flag written by EFIFO 0
* [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
* [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
* output
* [6] efifoBytesync EFIFO output byte 0 synchronization
* [5] rxinvalid 8b/10b error or 0 or code violation
* [4] rxinitdone Receiver bit-init done. 0 Synchronous with
* pipeClk.
* [3] txinitdone Transmitter-bit init done. 0 Synchronous with
* pipeClk.
* [2] filteredrxlos Filtered loss of signal used 1 to generate
* p2lRxelectidle. Synchronous with pipeClk.
* [1] rxdetectInt Receiver detected 0
* [0] pipeMasterDoneOut Receiver detection valid 0
*
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeDebug3
* PIPE Debug, status register
* Description: This register returns bits [127:96] of the PIPE
* core's gbtDebug bus
* Fields:
* The value specified here is the Power On Reset value as given
* in spec.
* This 16-bit debug bus reports operating conditions for the
* PIPE. The pipeDebug[0:15] bus is provided for each lane. lane0
* is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
* lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
* bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
* Refer to section 4.2.1.5 Single-Lane PIPE Debug Signals in
* the following document :
* cw000411TechMan.pdf
* lane6 is bits[111:96], which is pipeDebug3[15:0] lane7 is
* bits[127:112], which is pipeDebug3[31:16]
*
* -------------------------------------------------------------------------
* pipeDebug Signal or Condition Description Reset
* -------------------------------------------------------------------------
* [15] efifoOverflow or EFIFO overflow or 0 efifoUnderflow EFIFO
* underflow occurred
* [14] skipInsert or EFIFO skip inserted or 0 skipDelete
* deleted 0
* [13] fifordData[12] == Skip flag read by EFIFO. 0 skipFlag
* Used with skipcharflag to verify EFIFO depth.
* [12] skipcharflag Skip flag written by EFIFO 0
* [11:8] efifoDepth[3:0] Indicates EFIFO depth 0000
* [7] efifoEios Detected EFIFO 0 electrical-idle ordered-set
* output
* [6] efifoBytesync EFIFO output byte 0 synchronization
* [5] rxinvalid 8b/10b error or 0 or code violation
* [4] rxinitdone Receiver bit-init done. 0 Synchronous with
* pipeClk.
* [3] txinitdone Transmitter-bit init done. 0 Synchronous with
* pipeClk.
* [2] filteredrxlos Filtered loss of signal used 1 to generate
* p2lRxelectidle. Synchronous with pipeClk.
* [1] rxdetectInt Receiver detected 0
* [0] pipeMasterDoneOut Receiver detection valid 0
*
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PcieEnhCapHdr
* PCIE Enhanced Capability Header
* Description: PCIE Enhanced Capability Header
* Fields:
* Next Capability Offset (END, no more)
* Capability Version
* PCI Express Enhanced Capability ID (0x1 = Advanced Error
* Reporting)
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: UncErrStat
* Uncorrectable Error Status
* Description: Uncorrectable Error Status
* Fields:
* Unsupported Request Error
* ECRC Error
* Malformed TLP
* Reciever Overflow
* Unexpected Completion
* Completion Abort
* Completion Timeout
* Flow Control Protocol Error
* Poisoned TLP
* Introduced in PCIe 1.1 specification.
* Data Link Protocol Error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: UncErrMask
* Uncorrectable Error Mask
* Description: Uncorrectable Error Mask
* Fields:
* Unsupported Request Error
* ECRC Error
* Malformed TLP
* Reciever Overflow
* Unexpected Completion
* Completion Abort
* Completion Timeout
* Flow Control Protocol Error
* Poisoned TLP
* Introduced in PCIe 1.1
* Data Link Protocol Error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: UncErrSvrty
* Uncorrectable Error Severity
* Description: Uncorrectable Error Severity
* Fields:
* Unsupported Request Error
* ECRC Error
* Malformed TLP
* Reciever Overflow
* Unexpected Completion
* Completion Abort
* Completion Timeout
* Flow Control Protocol Error
* Poisoned TLP
* Introduced in PCIe 1.1 specification. Not supported; use PCIe
* default.
* Data Link Protocol Error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CorrErrStat
* Correctable Error Status
* Description: Correctable Error Status
* Fields:
* Advisory Non-Fatal Error Introduced in PCIe 1.1 specification.
* Reply Timer Timeout
* Replay Number Rollover
* Bad DLLP
* Bad TLP
* Receive Error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CorrErrMask
* Correctable Error Mask
* Description: Correctable Error Mask
* Fields:
* Advisory Non Fatal Error Mask
* Reply Timer Timeout
* Replay Number Rollover
* Bad DLLP
* Bad TLP
* Receive Error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: AdvCapCtrl
* Advanced Capability and Control
* Description: Advanced Capability and Control
* Fields:
* ECRC Check Enable
* ECRC Check Capable
* ECRC Generation Enable
* ECRC Generation Capability
* First Error Pointer
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: HdrLog0
* Header Log0
* Description: Header Log0
* Fields:
* First DW of TLP header with error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} hdr_log0_t;
/*
* Register: HdrLog1
* Header Log1
* Description: Header Log1
* Fields:
* Second DW of TLP header with error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} hdr_log1_t;
/*
* Register: HdrLog2
* Header Log2
* Description: Header Log2
* Fields:
* Third DW of TLP header with error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} hdr_log2_t;
/*
* Register: HdrLog3
* Header Log3
* Description: Header Log3
* Fields:
* Fourth DW of TLP header with error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} hdr_log3_t;
/*
* Register: PipeRxTxControl
* 00 : ewrap : Enable wrapback test mode 01 : padLoopback :
* Enable Pad Serial Loopback test mode 10 : revLoopback : Enable
* Reverse Loopback test mode 11 : efifoLoopback : Enable PCI
* Express Slave loop back
* test x11 : No-error test. A full test of the transceiver 111 :
* Forced-error test. A full test of the transceiver with forced
* errors
* 1 : selects 20-bit mode 0 : selects 10-bit mode
* 1 : selects Tx 20-bit fifo mode
* 00 : 52 us (470 cycles) 01 : 53 us (720 cycles) 10 : 54 us
* (970 cycles) 11 : 55 us (1220 cycles)
* 1 : selects 20-bit mode 0 : selects 10-bit mode
* 1 : Enable receiver reference clocks
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeRxTxStatus
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeRxTxPwrCntl
* 1 : power down termination trimming circuit 0 : normal
* operation
* Power down PECL Clock buffer 1 : when a bit is 1, power down
* associated clock buffer cell 0 : normal operation
* Power down Transmit PLL 1 : when a bit is 1, power down
* associated Tx PLL circuit 0 : normal operation
* Power down Differential O/P Clock buffer 1 : when a bit is 1,
* power down associated differntial clock buffer that drives
* gbtClkoutN/p 0 : normal operation
* Power down Transmitter Analog section 1 : when a bit is 1,
* power down analog section of the associated Transmitter and
* the Tx buffer 0 : normal operation
* Power down RxLOS 1 : when a bit is 1, it powers down the Rx
* LOS circuitry for the associated serdes lanes 0 : normal
* operation
* Power down Receiver Analog section 1 : when a bit is 1, power
* down analog section of the associated Receiver and the Tx
* buffer 0 : normal operation
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeRxTxParam
* Tx Driver Emphasis
* Serial output Slew Rate Control
* Tx Voltage Mux control
* Tx Voltage Pulse control
* Output Swing setting
* Transmitter Clock generator pole adjust
* Transmitter Clock generator zero adjust
* Receiver Clock generator pole adjust
* Receiver Clock generator zero adjust
* Bias Control for factory testing and debugging
* Receiver LOS Threshold adjustment. This value is determined by
* LSI.
* Receiver Input Equalizer control
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeRxTxClock
* Reverse Loopback clock select 00 : gbtRbcAO 01 : gbtRbcBO 10 :
* gbtRbcCO 11 : gbtRbcDO
* Select Master Clock 100 : All lanes 000 : Lane A 001 : Lane B
* 010 : Lane C 011 : Lane D
* Transmit PLL Divider control
* Transmit Data rate control
* Receiver PLL Frequency control
* Bit rate control to enable bit doubling feature
* Reset Transmitter lane
* Reset Receiver lane
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeGlueCntl0
* Pipe Glue Control 0
* Lock to Bitstream Initialization Time
* RXLOS Test bit
* Electrical Idle Ordered set enable
* Enable RxLOS
* Enable Fast resync
* RxLOS Sample Interval
* RxLOS threshold
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeGlueCntl1
* Pipe Glue Control 1
* Receiver Trim Resistance Configuration
* Transmitter Trim Resistance Configuration
* Auto Trim Enable
* 50 Ohm Termination Enable
* Customer select for reference clock frequency
* EFIFO Same clock select
* EFIFO start depth
* Lock to refclk initialization time
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: HcrReg
* HCR Registers
* Description: Hydra Specific Configuration Registers for use by
* software. These registers are loaded with the SPROM contents at
* power on. A maximum of 128 DWords has been assigned for s/w to
* use. This space generally stores the following informations : MAC
* Address Number of MAC addresses MAC Phy Type Other data fields are
* upto the software to use.
*
* Fields:
* Hydra specific configuration controlled by software
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} hcr_reg_t;
/*
* Register: BlockReset
* Block Reset
* Description: Soft resets to modules. Blade domain modules are
* reset by setting the corresponding block reset to 1. Shared domain
* resets are sent to SPI for processing and corresponding action by
* SPI. Shared domains are reset only if all the blades have
* requested a reset for that block. Below is an example scenario :
* s/w initiates the reset by writing '1' to the dpmRst bit dpmRst
* bit remains '1' until dpmRstStat is detected to be 1. Once
* dpmRstStat is detected to be 1, even if s/w writes 1 to this bit
* again no new reset will be initiated to the shared domain, ie,
* DPM. dpmRstStat is driven by external i/f (shared domain status
* provided by SPI) dpmRstStat bit will show '1' as long as the input
* stays at 1 or until s/w reads the status and is cleared only after
* s/w reads it and if dpmRstStat is 0 by then.
* If Host wants to reset entire Hydra it should do so through the
* mailbox. In this case, the message interprettation is upto the
* software. Writing a '1' to any of these bits generates a single
* pulse to the SP module which then controls the reset of the
* respective block.
*
* Fields:
* 1 : indicates that an active reset has been applied to the SP
* based on the request from all of the blades. Clears on Read
* provided the reset to SP has been deasserted by then by SPI.
* Setting to 1 allows this blade to request Service Processor
* (Shared) reset. However, SP reset can only occur if all blades
* agree. The success of reset request is indicated by spRstStat
* = 1 which is wired-AND of request from all the blades. Current
* request can be removed by writing a '0' to this bit. This bit
* clears automatically on detecting spRstStat = 1.
* Enable blade to service processor (Shared) reset voter
* registration = 1, disabled = 0
* Issue power reset to the EP Core Clears to 0, writing 0 has no
* effect.
* Issue core reset to the EP Core Clears to 0, writing 0 has no
* effect.
* Issue system reset (sysPor) to the PIPE Core This issues reset
* to the EP core, PCIe domains of Tdc, Rdc, and CIP. This shuts
* down the PCIe clock until Pipe core comes out of reset. The
* status of the Pipe core can be read by reading out the
* cipLinkStat register's pipe core status and pcie reset status
* bits. Clears to 0, writing 0 has no effect.
* 1 : indicates that an active reset has been applied to the
* NMAC based on the request from all of the blades. Clears on
* Read provided the reset to NMAC has been deasserted by then by
* SPI.
* 1 : indicates that an active reset has been applied to the TDP
* based on the request from all of the blades. Clears on Read
* provided the reset to TDP has been deasserted by then by SPI.
* 1 : indicates that an active reset has been applied to the DPM
* based on the request from all of the blades. Clears on Read
* provided the reset to DPM has been deasserted by then by SPI.
* This bit is effective only if sharedVoterEn (bit 24 of this
* reg) has been enabled. Writing '1' sends a request to SP to
* reset NMAC if sharedVoterEn=1. Intended for backdoor access.
* The success of reset request is indicated by nmacRstStat = 1
* which is wired-AND of request from all the blades. This also
* means that the reset request is successful only if all the
* blades requested for reset of this block. Current request can
* be removed by writing a '0' to this bit. This bit clears
* automatically on detecting nmacRstStat = 1.
* This bit is effective only if sharedVoterEn (bit 24 of this
* reg) has been enabled. Writing '1' sends a request to SP to
* reset TDP if sharedVoterEn=1. Intended for backdoor access.
* Intended for backdoor access. The success of reset request is
* indicated by tdpRstStat = 1 which is wired-AND of request from
* all the blades. This also means that the reset request is
* successful only if all the blades requested for reset of this
* block. Current request can be removed by writing a '0' to this
* bit. This bit clears automatically on detecting tdpRstStat =
* 1.
* This bit is effective only if sharedVoterEn (bit 24 of this
* reg) has been enabled. Writing '1' sends a request to SP to
* reset DPM if sharedVoterEn=1. Intended for backdoor access.
* Intended for backdoor access. The success of reset request is
* indicated by dpmRstStat = 1 which is wired-AND of request from
* all the blades. This also means that the reset request is
* successful only if all the blades requested for reset of this
* block. Current request can be removed by writing a '0' to this
* bit. This bit clears automatically on detecting dpmRstStat =
* 1.
* Setting to 1 generates tdcCoreReset and tdcPcieReset to the
* TDC block. The reset will stay asserted for atleast 4 clock
* cycles. Clears to 0, writing 0 has no effect.
* Setting to 1 generates rdcCoreReset and rdcPcieReset to the
* RDC block. The reset will stay asserted for atleast 4 clock
* cycles. Clears to 0, writing 0 has no effect.
* Setting to 1 generates reset to the PFC block. The reset will
* stay asserted for atleast 4 clock cycles. Clears to 0, writing
* 0 has no effect.
* Setting to 1 generates reset to the VMAC block. The reset will
* stay asserted for atleast 4 clock cycles. Clears to 0, writing
* 0 has no effect.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: TimeoutCfg
* PIO Timeout Configuration
* Description: PIO Timeout Configuration register to control wait
* time for a PIO access to complete. The timer resolution is in 250
* MHz clock.
* Fields:
* Programmable timeout counter value for PIO clients who did not
* ack a transaction in time. Minimum value should be 64.
* Timeout enable for PIO access to clients. 1 = enable.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: HeartCfg
* PIO Heartbeat Config
* Description: PIO Blade presence indication : Heartbeat
* configuration The timer resolution is in 250 MHz clock.
* Fields:
* Heartbeat countdown 250Mhz clock divider which serves as
* resolution for the heartTimer.
* Heartbeat countdown enable
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} heart_cfg_t;
/*
* Register: HeartTimer
* PIO Heartbeat Timer
* Description: PIO Blade presence indication : Heartbeat timer The
* timer resolution is in 250 MHz clock.
* Fields:
* Number of heartCfg.divider ticks of the 250Mhz clock before
* blade presence expires. This register decrements for every
* heartCfg.divider number of 250MHz clock cycles. It expires to
* 0 and so must be written periodically to reset the timer back
* to the required value. This counter does not have any effect
* on CIP functionality.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CipGpCtrl
* CIP General Purpose Control Register
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CipStatus
* CIP Status
* Description: This register returns CIP block's current logic
* status
* Fields:
* Current state of the cipEpc state machine 00 : epIdle ( wait
* for EEPROM request from SP or Host ) 01 : waitAck0 ( wait for
* ack from EEPROM for the first 16 bit read of the DW access )
* 11 : waitAck1 ( wait for ack from EEPROM for the second 16 bit
* state; EPC is never expected to be in this state )
* Current state of the cipSpc state machine 000 : spReset ( wait
* for Power-On SPROM download to start) 001 : getAddr ( Get
* CfgReg Address ) 010 : getData ( Get CfgReg Data ) 011 :
* ignoreData ( Address phase had an error, so ignore the Data
* coming in ) 100 : idleCyc ( Idle cycle following an AHB
* Address phase ) 101 : waitAck0 ( Wait for ack from EP Core
* during SPROM Download ) 110 : waitAck1 ( Wait for ack from EP
* PCI Bus Number as reported by EP core
* PCI Bus Device Number as reported by EP core
* 1: current csr access in progress is Local CIP csr access
* 1: current csr access in progress is Blade Domain csr access
* 1: a 64 bit blade domain access is in progress as two 32 bit
* accesses
* 1: indicates config values were downloaded from SPROM
* 1: indicates non-zero number of HCR config values downloaded
* from SPROM
* 1: indicates non-zero number of PCI config values downloaded
* from SPROM
* 1: indicates non-zero number of Pipe config values downloaded
* from SPROM
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} cip_status_t;
/*
* Register: CipLinkStat
* Link Status Register
* Description: This register returns the Link status
* Fields:
* NMAC XPCS-2 Link Status
* NMAC XPCS-1 Link Status
* NMAC XPCS-0 Link Status
* '1' indicates that pipe core went down suddenly when its reset
* sources are at deactivated level. When this happens, the PCIe
* domains. All these logics, EP Core, and the pipe core are held
* at reset until s/w writes 1 to this bit to clear status which
* will also bring the PCIe domain out of reset
* pipe core clock & reset status 1: core is up & running, ie,
* PIPE core is out of reset and clock is ON
* PCIe domain reset status 1: PCIe domain logics including EP
* core are out of reset; This also implies that PCIe clock is up
* and running
* EP Core XDM Link State
* EP Core RDM Link State
* EP Core LTSSM State
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: EpcStat
* EEPROM PIO Status
* Description: EEPROM PIO Status The Host may initiate access to the
* EEPROM either thru this register or directly by TRGT1 interfaces
* using ROM BAR access. Note that since the EEPROM can be accessed
* by either Host or SP, access must be granted to the PEU using the
* SPI PROM Control Register eepromPeuEn bit for proper operation.
* All EEPROM accesses initiated from either the Host or SP are
* always acknowledged. If a Host access is not acknowledged, then
* check the SPI PROM Control Register eepromPeuEn bit to make sure
* the PEU to EEPROM access has been enabled. Meanwhile, Host read
* and write accesses through the TRGT1 interface may be held up
* waiting for the acknowledgement. Thus, in order to recover from
* SP should configure the epcGotoNormal bit in the epcStat register.
* When Host accesses are stuck, only the SP can write into this bit
* to recover from this condition.
* The EEPROM is 1M x 16 bits or 2M bytes. The read address in bits
* [22:2] is byte address. The EEPROM access can only be DW access.
* While accessing through these registers, the lower 2 bits of the
* specified address is ignored resulting in a DW access to the
* EEPROM controller. While accessing through the ROM BAR range, only
* DW accesses are accepted and all other accesses will result in
* error status returned to the host.
* The read will initiate two reads to the EPC and the accumulated
* 32 bit data is returned to the Host either via the Client2 bus or
* in the epcData register depending on the cause of the transaction.
* This means, a read addr=0,1,2,3 will return data from EPC
* locations 0 & 1 which are 16 bits each, and a read to addr=4,5,6,7
* will return data from EPC locations 2,3 which are 16 bits each.
* Some examples for the address translation : 1) when Host gives
* address 0x0000, it means to get bytes 0,1,2, and 3 from the
* EEPROM. These bytes are stored at locations 0x0000 (bytes 0,1) and
* 0x0001 (bytes 2,3) in EEPROM. Hence PEU will present address
* 0x0000 followed by 0x0001 to the EEPROM.
* 2) when Host gives address 0x0004, it means to get bytes 4,5,6,
* and 7 from the EEPROM. These bytes are stored at locations 0x0002
* (bytes 4,5) and 0x0003 (bytes 6,7) in EEPROM. Hence PEU will
* present address 0x0002 followed by 0x0003 to the EEPROM.
* etc ..
*
* Fields:
* Force the EPC state machine to go to epIdle state. This bit is
* used to force the EPC to skip the reading of the EEPROM and
* goto the epIdle state which is normal state for EPC. The bit
* is auto-cleared after switching to the epIdle state. Both SP
* and HOST can write into this bit. However care must be taken
* writing '1' into this bit since setting this bit will flush
* out any pending EEPROM access request from Host. Hence, this
* bit should be used only if the EPC State machine (cipEpcSm
* bits in cipStatus register) is stuck at a non-zero state.
* EEPROM Byte Address for read operation This field can be
* updated only if there is no pending EEPROM read access.
* Software should poll bit 0 of this register (epcRdInit) to
* make sure that it is '0' before writing into this. If polled
* epcRdInit value is '1', then write to epcAddr field is
* ignored. This is to safe-guard the epcAddr value which is
* being read out the EEPROM.
* Read access completion status; set to '0' for successful
* completion by EPC set to '1' to indicate read access error
* from EPC
* Note: Currently, the EEPROM controller in Hydra does not
* return any error condition, ie, epcPeuErr = 1'b0 always. And
* so, for the PIO read access by the Host, the epcStat register
* in PEU will always show that the access was successful. For
* EEPROM read initiated through the ROM BAR by the Host, CIP
* will always return Successful Completion status to the Host.
* Any error situation is reported only in the Status Register
* within the EEPROM device. For access information about this
*
* Read Initiate. SW writes 1 to this bit to initiate a EEPROM
* read. Clears to 0 on updating the epcData reg. Writing 0 has
* no effect.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} epc_stat_t;
/*
* Register: EpcData
* EEPROM PIO Data
* Description: EEPROM PIO Data The data returned from EEPROM
* controller for the EEPROM access initiated by the EEPROM PIO
* Status register is returned in this register.
* Fields:
* EEPROM Read Data; valid when rdInit transitioned from 1 to 0.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} epc_data_t;
/*
* Register: SpcStat
* SPROM PIO Status
* Description: SPROM PIO Status
* Fields:
* Force the SPC state machine to go to NORMAL state. This bit is
* used to force the SPC to skip the downloading of the SPROM
* The bit is auto-cleared after switching to the Normal state.
* This bit can not be used to terminate a pio access to
* not responded to, by the respective block, then the pio access
* will automatically timeout. The timeout value is specified by
* the timeoutCfg:tmoutCnt value
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} spc_stat_t;
/*
* Register: Host2spiIndaccAddr
* HOST -> SPI Shared Domain Read Address
* Description: Read address set by Host for indirect access to
* shared domain address space The decoding of the address is as
* follows: [23:20] - block select [19:0] - register offset from base
* address of block
* Fields:
* Address in Shared domain
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: Host2spiIndaccCtrl
* HOST -> SPI Shared Domain Read Control
* Description: Control word set by Host for indirect access to the
* shared domain address space Writing to this register initiates the
* indirect access to the shared domain.
* The Host may read or write to a shared domain region data as
* below : Host updates the host2spiIndaccAddr register with address
* of the shared domain reg. For writes, Host updates the
* host2spiIndaccData register with write data Host then writes to
* bit 0 of host2spiIndaccCtrl register to '1' or '0' to initiate the
* read or write access; 1 : write command, 0 : read command Host
* should then poll bit 1 of host2spiIndaccCtrl register for the
* access status. 1 : access is done, 0 : access is in progress
* (busy) Host should then check bit 2 of host2spiIndaccCtrl register
* to know if the command was successful; 1 : access error, 0 :
* access successful For reads, Host then reads the
* host2spiIndaccData register for the read data.
* This register can be written into only when there is no pending
* access, ie, indaccCtrl.cplStat=1. Writes when indaccCtrl.cplStat=0
* is ignored.
*
* Fields:
* command completion status; 0 : successful completion of
* command by SPI 1 : access error from SPI
* command progress status; 0 : access is in progress (busy) 1 :
* access is done
* 1 : Initiate a write access 0 : Initiate a read access
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: Host2spiIndaccData
* Description: For indirect read access by the Host, this register
* returns the data returned from the Shared Domain For indirect
* write access by the Host, the host should update this register
* with the writeData for the Shared Domain, before writing to the
* host2spiIndaccCtrl register to initiate the access.
* This register can be written into only when there is no pending
* access, ie, indaccCtrl.cplStat=1. Writes when indaccCtrl.cplStat=0
* is ignored.
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: BtCtrl0
* Mailbox Control & Access status 0
* Description: Host (blade) <-> SP Block Transfer mailbox control
* and access status register 0.
* the same, it should provide the btCtrl0 address, data on
* hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
* provide the btCtrl0 address, data on spiDataBus[7:0], and no need
* of spiBen
*
* Fields:
* not accept any other request; write 1 to toggle the bit; Read
* Only by Host.
* can not accept any other request; Read Only by SP.
* Reserved for definition by platform. Typical usage could be
* interrupt the SP and then polls it to be cleared by SP
* The SP sets this bit when it has detected and queued an SMS
* message in the SP2HOST buffer that must be reported to the
* HOST. The Host clears this bit by writing a 1 to it. This bit
* may generate an intrpt to Host depending on the sp2hostIntEn
* bit. Writing 0 has no effect
* The SP writes 1 to this bit after it has finished writing a
* message into the SP2HOST buffer. The Host clears this bit by
* writing 1 to it after it has set the hostBusy bit This bit may
* generate an intrpt to Host depending on the sp2hostIntEn bit.
* Writing 0 has no effect
* The Host writes 1 to this bit to generate an interrupt to SP
* after it has finished writing a message into the HOST2SP
* buffer. The SP clears this bit by writing 1 to it after it has
* set the spBusy bit. Writing 0 has no effect
* The host writes 1 to clear the read pointer to the BT SP2HOST
* buffer; the SP writes 1 to clear the read pointer to the BT
* HOST2SP buffer. This bit is always read back as 0; writing 0
* has no effect.
* The host writes 1 to clear the write pointer to the BT HOST2SP
* buffer; the SP writes 1 to clear the write pointer to the BT
* SP2HOST buffer. This bit is always read back as 0; writing 0
* has no effect.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_ctrl0_t;
/*
* Register: BtData0
* Mailbox Data 0
* Description: Host (blade) <-> SP mailbox data register 0.
* do the same, it should provide the btData0 address, data on
* hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
* should provide the btData0 address, data on spiDataBus[7:0], and
* no need of spiBen
* All references to the mail box control bits in this register
* refer to btCtrl0. When spBusy=0 && host2spAtn=0, data is written
* by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0,
* data is written by the SP and read by the Host.
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_data0_t;
/*
* Register: BtIntmask0
* Mailbox Interrupt Mask & Status 0
* Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
* Status register 0
* the same, it should provide the btIntmask0 address, data on
* hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
* read only access to this register ; To do the same, it should
* provide the btIntmask0 address and no need of spiBen
* All references to the mail box control bits in this register
* refer to btCtrl0
* Fields:
* The host writes 1 to reset the entire mailbox 0 accesses for
* error recovery; resets both SP and HOST write and read
* pointers. Writing 0 has no effect. This is non-sticky. Always
* read back as 0.
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* SP to HOST Interrupt status This bit reflects the state of the
* intrpt line to the Host. O/S driver should write 1 to clear.
* SP to HOST Interrupt Enable The interrupt is generated if
* sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: BtCtrl1
* Mailbox Control & Access status 1
* Description: Host (blade) <-> SP Block Transfer mailbox control
* and access status register 1.
* the same, it should provide the btCtrl1 address, data on
* hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
* provide the btCtrl1 address, data on spiDataBus[7:0], and no need
* of spiBen
*
* Fields:
* can not accept any other request; write 1 to toggle the bit;
* Read only by Host.
* can not accept any other request; Read only by SP.
* Reserved for definition by platform. Typical usage could be
* interrupt the SP and then polls it to be cleared by SP
* The SP sets this bit when it has detected and queued an SMS
* message in the SP2HOST buffer that must be reported to the
* HOST. The Host clears this bit by writing a 1 to it. This bit
* may generate an intrpt to Host depending on the sp2hostIntEn
* bit. Writing 0 has no effect
* The SP writes 1 to this bit after it has finished writing a
* message into the SP2HOST buffer. The Host clears this bit by
* writing 1 to it after it has set the hostBusy bit This bit may
* generate an intrpt to Host depending on the sp2hostIntEn bit.
* Writing 0 has no effect
* The Host writes 1 to this bit to generate an interrupt to SP
* after it has finished writing a message into the HOST2SP
* buffer. The SP clears this bit by writing 1 to it after it has
* set the spBusy bit. Writing 0 has no effect
* The host writes 1 to clear the read pointer to the BT SP2HOST
* buffer; the SP writes 1 to clear the read pointer to the BT
* HOST2SP buffer. This bit is always read back as 0; writing 0
* has no effect.
* The host writes 1 to clear the write pointer to the BT HOST2SP
* buffer; the SP writes 1 to clear the write pointer to the BT
* SP2HOST buffer. This bit is always read back as 0; writing 0
* has no effect.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_ctrl1_t;
/*
* Register: BtData1
* Mailbox Data 1
* Description: Host (blade) <-> SP mailbox data register 1.
* do the same, it should provide the btData1 address, data on
* hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
* should provide the btData1 address, data on spiDataBus[7:0], and
* no need of spiBen
* All references to the mail box control bits in this register
* refer to btCtrl1. When spBusy=0 && host2spAtn=0, data is written
* by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0,
* data is written by the SP and read by the Host.
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_data1_t;
/*
* Register: BtIntmask1
* Mailbox Interrupt Mask & Status 1
* Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
* Status register 1
* the same, it should provide the btIntmask1 address, data on
* hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
* read only access to this register ; To do the same, it should
* provide the btIntmask1 address and no need of spiBen
* All references to the mail box control bits in this register
* refer to btCtrl1
* Fields:
* The host writes 1 to reset the entire mailbox 1 accesses for
* error recovery; resets both SP and HOST write and read
* pointers. Writing 0 has no effect. This is non-sticky. Always
* read back as 0.
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* SP to HOST Interrupt status This bit reflects the state of the
* intrpt line to the Host. O/S driver should write 1 to clear.
* SP to HOST Interrupt Enable The interrupt is generated if
* sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: BtCtrl2
* Mailbox Control & Access status 2
* Description: Host (blade) <-> SP Block Transfer mailbox control
* and access status register 2.
* the same, it should provide the btCtrl2 address, data on
* hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
* provide the btCtrl2 address, data on spiDataBus[7:0], and no need
* of spiBen
*
* Fields:
* can not accept any other request; write 1 to toggle the bit;
* Read only by Host.
* can not accept any other request; Read only by SP.
* Reserved for definition by platform. Typical usage could be
* interrupt the SP and then polls it to be cleared by SP
* The SP sets this bit when it has detected and queued an SMS
* message in the SP2HOST buffer that must be reported to the
* HOST. The Host clears this bit by writing a 1 to it. This bit
* may generate an intrpt to Host depending on the sp2hostIntEn
* bit. Writing 0 has no effect
* The SP writes 1 to this bit after it has finished writing a
* message into the SP2HOST buffer. The Host clears this bit by
* writing 1 to it after it has set the hostBusy bit This bit may
* generate an intrpt to Host depending on the sp2hostIntEn bit.
* Writing 0 has no effect
* The Host writes 1 to this bit to generate an interrupt to SP
* after it has finished writing a message into the HOST2SP
* buffer. The SP clears this bit by writing 1 to it after it has
* set the spBusy bit. Writing 0 has no effect
* The host writes 1 to clear the read pointer to the BT SP2HOST
* buffer; the SP writes 1 to clear the read pointer to the BT
* HOST2SP buffer. This bit is always read back as 0; writing 0
* has no effect.
* The host writes 1 to clear the write pointer to the BT HOST2SP
* buffer; the SP writes 1 to clear the write pointer to the BT
* SP2HOST buffer. This bit is always read back as 0; writing 0
* has no effect.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_ctrl2_t;
/*
* Register: BtData2
* Mailbox Data 2
* Description: Host (blade) <-> SP mailbox data register 2. All
* references to the mail box control bits in this register refer to
* btCtrl2.
* do the same, it should provide the btData2 address, data on
* hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
* should provide the btData2 address, data on spiDataBus[7:0], and
* no need of spiBen
* When spBusy=0 && host2spAtn=0, data is written by the host and
* read by the SP. When hostBusy=0 && sp2hostAtn=0, data is written
* by the SP and read by the Host.
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_data2_t;
/*
* Register: BtIntmask2
* Mailbox Interrupt Mask & Status 2
* Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
* Status register 2
* the same, it should provide the btIntmask2 address, data on
* hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
* read only access to this register ; To do the same, it should
* provide the btIntmask2 address and no need of spiBen
* All references to the mail box control bits in this register
* refer to btCtrl2
* Fields:
* The host writes 1 to reset the entire mailbox 2 accesses for
* error recovery; resets both SP and HOST write and read
* pointers. Writing 0 has no effect. This is non-sticky. Always
* read back as 0.
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* SP to HOST Interrupt status This bit reflects the state of the
* intrpt line to the Host. O/S driver should write 1 to clear.
* SP to HOST Interrupt Enable The interrupt is generated if
* sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: BtCtrl3
* Mailbox Control & Access status 3
* Description: Host (blade) <-> SP Block Transfer mailbox control
* and access status register 3.
* the same, it should provide the btCtrl3 address, data on
* hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
* provide the btCtrl3 address, data on spiDataBus[7:0], and no need
* of spiBen
*
* Fields:
* can not accept any other request; write 1 to toggle the bit;
* Read only by Host.
* can not accept any other request; Read only by SP.
* Reserved for definition by platform. Typical usage could be
* interrupt the SP and then polls it to be cleared by SP
* The SP sets this bit when it has detected and queued an SMS
* message in the SP2HOST buffer that must be reported to the
* HOST. The Host clears this bit by writing a 1 to it. This bit
* may generate an intrpt to Host depending on the sp2hostIntEn
* bit. Writing 0 has no effect
* The SP writes 1 to this bit after it has finished writing a
* message into the SP2HOST buffer. The Host clears this bit by
* writing 1 to it after it has set the hostBusy bit This bit may
* generate an intrpt to Host depending on the sp2hostIntEn bit.
* Writing 0 has no effect
* The Host writes 1 to this bit to generate an interrupt to SP
* after it has finished writing a message into the HOST2SP
* buffer. The SP clears this bit by writing 1 to it after it has
* set the spBusy bit. Writing 0 has no effect
* The host writes 1 to clear the read pointer to the BT SP2HOST
* buffer; the SP writes 1 to clear the read pointer to the BT
* HOST2SP buffer. This bit is always read back as 0; writing 0
* has no effect.
* The host writes 1 to clear the write pointer to the BT HOST2SP
* buffer; the SP writes 1 to clear the write pointer to the BT
* SP2HOST buffer. This bit is always read back as 0; writing 0
* has no effect.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_ctrl3_t;
/*
* Register: BtData3
* Mailbox Data 3
* Description: Host (blade) <-> SP mailbox data register 3.
* do the same, it should provide the btData3 address, data on
* hostDataBus[31:0], and assert hostBen[1], SPI is allowed only 8
* should provide the btData3 address, data on spiDataBus[7:0], and
* no need of spiBen
* All references to the mail box control bits in this register
* refer to btCtrl3. When spBusy=0 && host2spAtn=0, data is written
* by the host and read by the SP. When hostBusy=0 && sp2hostAtn=0,
* data is written by the SP and read by the Host.
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} bt_data3_t;
/*
* Register: BtIntmask3
* Mailbox Interrupt Mask & Status 3
* Description: Host (blade) <-> SP Block Transfer Interrupt Mask and
* Status register 3
* the same, it should provide the btIntmask3 address, data on
* hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
* read only access to this register ; To do the same, it should
* provide the btIntmask3 address and no need of spiBen
* All references to the mail box control bits in this register
* refer to btCtrl3
* Fields:
* The host writes 1 to reset the entire mailbox 3 accesses for
* error recovery; resets both SP and HOST write and read
* pointers. Writing 0 has no effect. This is non-sticky. Always
* read back as 0.
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* Handler use. Generic IPMI software must write this bit as 0
* and ignore the value on read
* SP to HOST Interrupt status This bit reflects the state of the
* intrpt line to the Host. O/S driver should write 1 to clear.
* SP to HOST Interrupt Enable The interrupt is generated if
* sp2hIrqEn is 1 and either sp2hostAtn or smsAtn is 1
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: DebugSel
* CIP Debug Data Select
* Description: Selects the debug data signals from the CIP blocks
* Fields:
* peuPhyVdbgDebugPort[31:0]
* Selects the high DW of the debug data - default is PCIe link
* status
* Selects the low DW of the debug data
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} debug_sel_t;
/*
* Register: IndaccMem0Ctrl
* CIP Mem0 Debug ctrl
* Description: Debug data signals from the CIP blocks
* Fields:
* 1: pkt injection is done 0: pkt injection is in progress
* Ingress pkt injection enable: write to 1 for single pkt
* memories.
* injection.
* 1: read, 0: write
* mem0Diagen bit is also written with '1' along with enabling
* this bit. Else, the write will not have any effect. 1: Apply
* the parity mask provided in the Prty register 0: Do not apply
* the parity mask provided in the Prty register
* 0 : select npdataq memory 1 : select nphdrq memory 2 : select
* pdataq memory 3 : select phdrq memory 4 : select cpldataq
* memory 5 : select cplhdrq memory
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem0Data0
* CIP Mem0 Debug Data0
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem0Sel bits from mem0Ctrl This data is written to
* the memory when indaccMem0Ctrl register is written with the
* write command When indaccMem0Ctrl register is written with the
* read command, this register will hold the Data[31:0] returned
* from the memory When pktInjectionEnable is 1:
* debugData0Reg[31:0] is used in the following ways: [17:16] =
* radmTrgt1Fmt[1:0]: 2'b00 3DW MRd 2'b01 4DW MRd 2'b10 3DW MWr
* 2'b11 4DW MWr [13:12] = radmTrgt1DwLen[1:0]: 2'b01 1DW 2'b10
* 2DW [11:8] = radmTrgt1LastBe[3:0]: 4'b0000 1DW 4'b1111 2DW [7]
* = radmTrgt1RomInRange 1'b0 PIO Access 1'b1 EEPROM Access [6:4]
* = radmTrgt1InMembarRange[2:0] 3'b000 PIO Access 3'b010 MSIX
* 1DW->last DW is at radmTrgt1Data[31:0] 2'b11 2DW->last DW is
* at radmTrgt1Data[63:32]
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem0Data1
* CIP Mem0 Debug Data1
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem0Sel bits from mem0Ctrl This data is written to
* the memory when indaccMem0Ctrl register is written with the
* write command When indaccMem0Ctrl register is written with the
* read command, this register will hold the Data[63:32] returned
* from the memory When pktInjectionEnable is 1:
* debugData1Reg[31:0] is used as radmTrgt1Addr[31:0].
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem0Data2
* CIP Mem0 Debug Data2
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem0Sel bits from mem0Ctrl This data is written to
* the memory when indaccMem0Ctrl register is written with the
* write command When indaccMem0Ctrl register is written with the
* read command, this register will hold the Data[95:64] returned
* from the memory When pktInjectionEnable is 1:
* debugData2Reg[31:0] is used as radmTrgt1Data[63:32]. Allows up
* to QW=2DW access.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem0Data3
* CIP Mem0 Debug Data3
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem0Sel bits from mem0Ctrl This data is written to
* the memory when indaccMem0Ctrl register is written with the
* write command When indaccMem0Ctrl register is written with the
* read command, this register will hold the Data[127:96]
* returned from the memory When pktInjectionEnable is 1:
* debugData3Reg[31:0] is used as radmTrgt1Data[31:0].
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem0Prty
* CIP Mem0 Debug Parity
* Description: Debug data signals from the CIP blocks
* Fields:
* parity mask bits for the memory selected by mem0Sel bits from
* mem0Ctrl to inject parity error These bits serve two purposes
* regarding memory parity : - During indirect write access to
* the memories, the value in this register is applied as mask to
* the actual parity if prtyWen bit of the indaccCtrl register
* has been enabled. The masked parity and data are written into
* the specified memory location. - During indirect read access
* to the memories, the value in this register is overwritten
* with the parity value read from the memory location. If the
* parity mask had been set and enabled to be written into this
* location it will generate parity error for that memory
* location
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem1Ctrl
* CIP Mem1 Debug ctrl
* Description: Debug data signals from the CIP blocks
* Fields:
* 1: client pkt injection is done 0: client pkt injection is in
* progress
* 1: client1 pkt injection 0: client0 pkt injection
* Mutually exclusive: Either client0 or client1 egress pkt
* injection enable: write to 1 for single pkt injection. Must be
* disabled Must be 0 when enabling pkt injection.
* 1: read, 0: write
* mem1Diagen bit is also written with '1' along with enabling
* this bit. Else, the write will not have any effect. 1: Apply
* the parity mask provided in the Prty register 0: Do not apply
* the parity mask provided in the Prty register
* 0 : select retry sot memory 1 : select retry buffer memory 2 :
* select msix memory 3 : select hcr cfg memory
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem1Data0
* CIP Mem1 Debug Data0
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem1Sel bits from mem1Ctrl This data is written to
* the memory when indaccMem1Ctrl register is written with the
* write command When indaccMem1Ctrl register is written with the
* read command, this register will hold the Data[31:0] returned
* from the memory
* When pktInjectionEnable is 1: debugData0Reg[31:0] is used in
* the following ways: [27:26] = tdcPeuTlp0[or
* rdcPeuTlp1]_fmt[1:0]: 2'b00 3DW MRd 2'b01 4DW MRd 2'b10 3DW
* MWr 2'b11 4DW MWr [25:13] = tdcPeuTlp0[or
* rdcPeuTlp1]_byteLen[12:0]: Note MWr must be limited to 4B =
* 13'b0000000000001. [12:8] = tdcPeuTlp0[or
* rdcPeuTlp1]_tid[4:0]: 5 lsb of tid (TAG ID) [7:0] =
* tdcPeuTlp0[or rdcPeuTlp1]_byteEn[7:0]: [7:4] = last DW byte
* enables [3:0] = first DW byte enables
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem1Data1
* CIP Mem1 Debug Data1
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem1Sel bits from mem1Ctrl This data is written to
* the memory when indaccMem1Ctrl register is written with the
* write command When indaccMem1Ctrl register is written with the
* read command, this register will hold the Data[63:32] returned
* from the memory
* When pktInjectionEnable is 1: debugData1Reg[31:0] is used as
* tdcPeuTlp0[or rdcPeuTlp1]_addr[63:32] high address bits.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem1Data2
* CIP Mem1 Debug Data2
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem1Sel bits from mem1Ctrl This data is written to
* the memory when indaccMem1Ctrl register is written with the
* write command When indaccMem1Ctrl register is written with the
* read command, this register will hold the Data[95:64] returned
* from the memory
* When pktInjectionEnable is 1: debugData2Reg[31:0] is used as
* tdcPeuTlp0[or rdcPeuTlp1]_addr[31:0] low address bits.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem1Data3
* CIP Mem1 Debug Data3
* Description: Debug data signals from the CIP blocks
* Fields:
* selected by mem1Sel bits from mem1Ctrl This data is written to
* the memory when indaccMem1Ctrl register is written with the
* write command When indaccMem1Ctrl register is written with the
* read command, this register will hold the Data[127:96]
* returned from the memory
* When pktInjectionEnable is 1: debugData3Reg[31:0] is used as
* tdcPeuTlp0[or rdcPeuTlp1]_data[31:0] Limited for MWr to 1 DW.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: IndaccMem1Prty
* CIP Mem1 Debug Parity
* Description: Debug data signals from the CIP blocks
* Fields:
* parity mask bits for the memory selected by mem1Sel bits from
* mem1Ctrl to inject parity error These bits serve two purposes
* regarding memory parity : - During indirect write access to
* the memories, the value in this register is applied as mask to
* the actual parity if prtyWen bit of the indaccCtrl register
* has been enabled. The masked parity and data are written into
* the specified memory location. - During indirect read access
* to the memories, the value in this register is overwritten
* with the parity value read from the memory location. If the
* parity mask had been set and enabled to be written into this
* location it will generate parity error for that memory
* location
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PhyDebugTrainingVec
* peuPhy Debug Training Vector
* Description: peuPhy Debug Training Vector register.
* Fields:
* Hard-coded value for peuPhy wrt global debug training block
* signatures.
* Blade Number, the value read depends on the blade this block
* resides
* debug training vector the sub-group select value of 0 selects
* this vector
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PeuDebugTrainingVec
* PEU Debug Training Vector
* Description: PEU Debug Training Vector register.
* Fields:
* Hard-coded value for PEU (VNMy - core clk domain) wrt global
* debug training block signatures.
* Blade Number, the value read depends on the blade this block
* resides
* debug training vector the sub-group select value of 0 selects
* this vector
* Hard-coded value for PEU (VNMy - core clk domain) wrt global
* debug training block signatures.
* Blade Number, the value read depends on the blade this block
* resides
* debug training vector the sub-group select value of 0 selects
* this vector
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PipeCfg0
* PIPE Configuration
* Description: These are controls signals for the pipe core and are
* used to define the PIPE core configuration with PipeCfg1 reg value
* (0x08124)
* Fields:
* If this bit is 1 when pipe reset is released, then the value
* on the pipe core's input port 'pipeParameter' is loaded into
* pipeRxTxParam at addr 0x01010. Note that it is software's
* responsibility to program the pipeParameter (Pipe Cfg1)
* register correctly: e.g. LOSADJ must be 0x1.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} pipe_cfg0_t;
/*
* Register: PipeCfg1
* PIPE Configuration
* Description: These values define the PIPE core configuration and
* is presented on the Pipe core's input port 'pipeParameter'.
* The value on the pipe core's input 'pipeParameter' is loaded into
* pipeRxTxParam at addr 0x01010, by forcing the pipeForceParm bit of
* the Pipe Cfg0 Register at address 0x08120.
*
* Fields:
* Tx Driver Emphasis
* Serial output Slew Rate Control
* Tx Voltage Mux control
* Tx Voltage Pulse control
* Output Swing setting
* Transmitter Clock generator pole adjust
* Transmitter Clock generator zero adjust
* Receiver Clock generator pole adjust
* Receiver Clock generator zero adjust
* Bias Control for factory testing and debugging
* Receiver LOS Threshold adjustment. LSI suggests this POR
* default value must be 0x1 (which is the POR default value of
* Receiver Input Equalizer control
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} pipe_cfg1_t;
/*
* Register: CipBarMaskCfg
* BAR Mask Config
* Description: To write to the BAR MASK registers in the EP Core PCI
* Config registers This register should be initialised before
* writing the value to into the cipBarMask register. The lower 3
* bits define the BAR register number whose mask value has to be
* over written with the values that will be written into the
* cipBarMask register. [2:0] = 0 thru 5 selects bar0Mask thru
* bar5Mask registers = 6,7 selects Expansion romBarMask register
* Hydra's configuration for the BARs is as below : BAR1, BAR0 :
* Forms 64 bit PIO BAR. BAR1 handles the upper address bits BAR0
* handles the lower address bits BAR3, BAR2 : Forms 64 bit MSIX BAR
* BAR3 handles the upper address bits BAR2 handles the lower address
* bits BAR5, BAR4 : Not used and so disabled. Hence, user writes
* will not have any effect. romBar : Expansion romBar
*
* Fields:
* 0 : bar0Mask 1 : bar1Mask 2 : bar2Mask 3 : bar3Mask 4 :
* bar4Mask 5 : bar5Mask 6, 7 ; romBarMask
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CipBarMask
* BAR Mask
* Description: Value to write to the BAR MASK registers in the EP
* Core PCI Config registers The lower 3 bits of cipMaskCfg register
* define the BAR register number Write to this register will
* initiate the DBI access to the EP Core. The cipBarMaskCfg register
* should be setup before writing to this register. [31:1] = Mask
* value [0] = 1: BAR is enabled; 0: BAR is disabled. Note that the
* BAR must be enabled ([0] == 1) before the Mask value will be
* written into the actual bar mask register. If the BAR is disabled
* ([0]==0), two writes to this register are required before the Mask
* value is written into the actual bar mask register. Refer to EP
* core data book for more details.
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CipLdsv0Stat
* LDSV0 Status (for debug purpose)
* Description: Returns the status of LDSV0 Flags regardless of their
* group
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CipLdsv1Stat
* LDSV1 Status (for debug purpose)
* Description: Returns the status of LDSV1 Flags regardless of their
* group
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PeuIntrStat
* PEU Interrupt Status
* Description: Returns the parity error status of all of the PEU
* RAMs, and external (to peu) block pio access errors. External
* block pio access errors could be due to either host or SPI
* initiated accesses. These fields are RO and can be cleared only
* through a cip reset All these errors feed to devErrStat.peuErr1
* which in turn feed to LDSV1.devErr1
* Partity Error bits: These bits log the very first parity error
* detected in a particular memory. The corresponding memory location
* is logged in respective perrLoc registers. External Block PIO
* Access Error bits: These bits log the very first error that
* resulted in access error. The corresponding address is logged in
* respective accErrLog registers.
* These bits can be set by writing a '1' to the corresponding
* mirror bit in the peuIntrStatMirror register.
* Note: PEU RAM Parity Errors and their corresponding interrupt:
* When these bits are set and the device error status interrupt is
* not masked, the PEU attempts to send the corresponding interrupt
* back to the RC. Depending on which ram is impacted and the
* corresponding logic impacted in the EP core, a coherent interrupt
* message may not be sent in all cases. For the times when the EP
* core is unable to send an interrupt, the SPI interface is to be
* used for error diagnosis as the PEU interrupt status is logged
* regardless of whether the interrupt is sent to the RC. The
* following data was collected via simulation: -Parity error
* impacted rams that likely will be able to send an interrupt:
* npDataq, pDataq, cplDataq, hcr. -Parity error impacted rams that
* may not be able to send an interrupt: npHdrq, pHdrq, cplHdrq, MSIx
* table, retryram, retrysot.
*
* Fields:
* Error indication from SPROM Controller for Sprom Download
* access This error indicates that a parity error was detected
* from SRAM. For more details, please refer to SPROM Controller
* PRM.
* Error indication from TDC for PIO access The error location
* and type are logged in tdcPioaccErrLog
* Error indication from RDC for PIO access The error location
* and type are logged in rdcPioaccErrLog
* Error indication from PFC for PIO access The error location
* and type are logged in pfcPioaccErrLog
* Error indication from VMAC for PIO access The error location
* and type are logged in vmacPioaccErrLog
* memory in PCIe data path and value unknown until packet flow
* starts.
* memory in PCIe data path and value unknown until packet flow
* starts.
* memory in PCIe data path and value unknown until packet flow
* starts.
* memory in PCIe data path and value unknown until packet flow
* starts.
* memory in PCIe data path and value unknown until packet flow
* starts.
* memory in PCIe data path and value unknown until packet flow
* starts.
* memory in PCIe data path and value unknown until packet flow
* starts.
* memory in PCIe data path and value unknown until packet flow
* starts.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PeuIntrMask
* Parity Error Status Mask
* Description: Masks for interrupt generation for block and parity
* error in the PEU RAMs For the VNM errors (spc, tdc, rdc, pfc, &
* vmac), note that the interrupt message to the host will be delayed
* from the actual moment that the error is detected until the host
* does a PIO access and this mask is cleared.
*
* Fields:
* 1: Mask interrupt generation for access error from SPROM
* Controller
* 1: Mask interrupt generation for PIO access error from TDC
* 1: Mask interrupt generation for PIO access error from RDC
* 1: Mask interrupt generation for PIO access error from PFC
* 1: Mask interrupt generation for PIO access error from VMAC
* 1: Mask interrupt generation for parity error from Completion
* Header Q memory
* 1: Mask interrupt generation for parity error from Completion
* Data Q memory
* 1: Mask interrupt generation for parity error from Retry
* memory
* 1: Mask interrupt generation for parity error from Retry SOT
* memory
* 1: Mask interrupt generation for parity error from Posted
* Header Q memory
* 1: Mask interrupt generation for parity error from Posted Data
* Q memory
* 1: Mask interrupt generation for parity error from Non-Posted
* Header Q memory
* 1: Mask interrupt generation for parity error from Non-Posted
* Data Q memory
* 1: Mask interrupt generation for parity error from MSIX memory
* 1: Mask interrupt generation for parity error from HCR memory
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PeuIntrStatMirror
* Parity Error Status Mirror
* Description: Mirror bits for Parity error generation in the PEU
* RAMs When set, the corresponding parity error is generated ; this
* will cause an interrupt to occur if the respective mask bit is not
* set. As the mirror of the Parity Error Status Register, clearing
* of the status bits is controlled by how the Parity Error Status
* Register is cleared. These bits cannot be cleared by writing 0 to
* this register.
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CplHdrqPerrLoc
* Completion Header Queue Parity Error Location
* Description: Returns the location of the first parity error
* detected in Completion Header Q
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: CplDataqPerrLoc
* Completion Data Queue Parity Error Location
* Description: Returns the location of the first parity error
* detected in Completion Data Q
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: RetrPerrLoc
* Retry RAM Parity Error Location
* Description: Returns the location of the first parity error
* detected in Retry RAM
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: RetrSotPerrLoc
* Retry SOT RAM Parity Error Location
* Description: Returns the location of the first parity error
* detected in Retry RAM SOT
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PHdrqPerrLoc
* Posted Header Queue Parity Error Location
* Description: Returns the location of the first parity error
* detected in Posted Header Q
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PDataqPerrLoc
* Posted Data Queue Parity Error Location
* Description: Returns the location of the first parity error
* detected in Posted Data Q
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: NpHdrqPerrLoc
* Non-Posted Header Queue Parity Error Location
* Description: Returns the location of the first parity error
* detected in Non-Posted Header Q
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: NpDataqPerrLoc
* Non-Posted Data Queue Parity Error Location
* Description: Returns the location of the first parity error
* detected in Non-Posted Data Q
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: MsixPerrLoc
* MSIX Parity Error Location
* Description: Returns the location of the first parity error
* detected in MSIX memory
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: HcrPerrLoc
* HCR Memory Parity Error Location
* Description: Returns the location of the first parity error
* detected in HCR Memory
*
* Fields:
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: TdcPioaccErrLog
* TDC PIO Access Error Location
* Description: Returns the location of the first transaction
* location that resulted in error
*
* Fields:
* Type of access error 0 : Block returned error condition 1 :
* Transaction resulted in time out by CIP
* Transaction Location that resulted in error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: RdcPioaccErrLog
* RDC PIO Access Error Location
* Description: Returns the location of the first transaction
* location that resulted in error
*
* Fields:
* Type of access error 0 : Block returned error condition 1 :
* Transaction resulted in time out by CIP
* Transaction Location that resulted in error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: PfcPioaccErrLog
* PFC PIO Access Error Location
* Description: Returns the location of the first transaction
* location that resulted in error
*
* Fields:
* Type of access error 0 : Block returned error condition 1 :
* Transaction resulted in time out by CIP
* Transaction Location that resulted in error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: VmacPioaccErrLog
* VMAC PIO Access Error Location
* Description: Returns the location of the first transaction
* location that resulted in error
*
* Fields:
* Type of access error 0 : Block returned error condition 1 :
* Transaction resulted in time out by CIP
* Transaction Location that resulted in error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: LdGrpCtrl
* Logical Device Group Control
* Description: LD Group assignment
* Fields:
* Logical device group number of this logical device
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: DevErrStat
* Device Error Status
* Description: Device Error Status logs errors that cannot be
* attributed to a given dma channel. It does not duplicate errors
* already observable via specific block logical device groups.
* Device Error Status bits [31:16] feed LDSV0.devErr0 Device Error
* Status bits [15:0] feed LDSV1.devErr1
* Fields:
* PEU.
* Set to 1 if RX Ctrl or Data FIFO has a single bit ecc error.
* This error condition is asserted by RDC to PEU.
* Set to 1 if any of the external block accesses have resulted
* in error or if a parity error was detected in the SPROM
* internal ram. Refer to peuIntrStat for the errors that
* contribute to this bit.
* PEU.
* Set to 1 if RX Ctrl or Data FIFO has a double bit ecc error.
* This error condition is asserted by RDC to PEU.
* has a parity error Refer to peuIntrStat for the errors that
* contribute to this bit.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: DevErrMask
* Device Error Mask
* Description: Device Error Mask (gates devErrStat)
* Fields:
* Mask for TDC error0
* Mask for RDC error0
* Mask for VNM PIO Access error
* Mask for TDC error1
* Mask for RDC error1
* Mask for PEU memories parity error
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: LdIntrTimRes
* Logical Device Interrupt Timer Resolution
* Description: Logical Device Interrupt Timer Resolution
* Fields:
* Timer resolution in 250 MHz cycles
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: LDSV0
* Logical Device State Vector 0
* Description: Logical Device State Vector 0
* Fields:
* Interrupt from mail box3 to HOST
* Interrupt from mail box2 to HOST
* Interrupt from mail box1 to HOST
* Interrupt from mail box0 to HOST
* Flag0 bits for Network MAC
* Flag0 bits for Virtual MAC
* Flag0 bits for Tx DMA channels 3-0
* Flag0 bits for Rx DMA channels 3-0
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} ldsv0_t;
/*
* Register: LDSV1
* Logical Device State Vector 1
* Description: Logical Device State Vector 1
* Fields:
* Flag1 bits for Network MAC
* Flag1 bits for Tx DMA channels 3-0
* Flag1 bits for Rx DMA channels 3-0
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} ldsv1_t;
/*
* Register: LdIntrMask
* Logical Device Interrupt Mask
* Description: Logical Device Interrupt Mask
* Fields:
* Flag1 mask for logical device N (0-31)
* Flag0 mask for logical device N (0-31)
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: LdIntrMgmt
* Logical Device Interrupt Management
* Description: Logical Device Interrupt Management
* Fields:
* SW arms the logical device for interrupt. Cleared by HW after
* interrupt issued. (1 = arm)
* Timer set by SW. Hardware counts down.
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
/*
* Register: SID
* System Interrupt Data
* Description: System Interrupt Data (MSI Vectors)
* Fields:
* Data sent along with the interrupt
*/
typedef union {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} sid_t;
#ifdef __cplusplus
}
#endif
#endif /* _HXGE_PEU_HW_H */