/*
* This file is provided under a CDDLv1 license. When using or
* redistributing this file, you may do so under this license.
* In redistributing this file this license must be included
* and no other modification of this header file is permitted.
*
* CDDL LICENSE SUMMARY
*
* Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
*
* The contents of this file are subject to the terms of Version
* 1.0 of the Common Development and Distribution License (the "License").
*
* You should have received a copy of the License with this software.
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDLv1.
*/
/*
* IntelVersion: 1.61 sol_anvik_patch
*/
extern "C" {
#endif
#
define E1000_CTRL 0x00000 /* Device Control - RW */#
define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */#
define E1000_FLA 0x0001C /* Flash Access - RW */#
define E1000_SCTL 0x00024 /* SerDes Control - RW */#
define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */#
define E1000_FCAH 0x0002C /* Flow Control Address High -RW */#
define E1000_FEXT 0x0002C /* Future Extended - RW */#
define E1000_FCT 0x00030 /* Flow Control Type - RW */#
define E1000_VET 0x00038 /* VLAN Ether Type - RW */#
define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */#
define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */#
define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */#
define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */#
define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */#
define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */#
define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */#
define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */#
define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */#
define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */#
define E1000_TBT 0x00448 /* Tx Burst Timer - RW */#
define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */#
define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */#
define E1000_PBS 0x01008 /* Packet Buffer Size */#
define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */#
define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */#
define E1000_FLOP 0x0103C /* FLASH Opcode Register */#
define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */#
define E1000_ERT 0x02008 /* Early Rx Threshold - RW */#
define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */#
define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */#
define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */#
define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */#
define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW *//* Split and Replication Rx Control - RW */
#
define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */#
define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */#
define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */#
define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */#
define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */#
define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */#
define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW *//*
* Convenience macros
*
* Note: "_n" is the queue number of the register to be written to.
*
* Example usage:
* E1000_RDBAL_REG(current_rx_queue)
*/
((
_n) <
4 ? (
0x02800 + ((
_n) *
0x100)) : (
0x0C000 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x02804 + ((
_n) *
0x100)) : (
0x0C004 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x02808 + ((
_n) *
0x100)) : (
0x0C008 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x0280C + ((
_n) *
0x100)) : (
0x0C00C + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x02810 + ((
_n) *
0x100)) : (
0x0C010 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x02818 + ((
_n) *
0x100)) : (
0x0C018 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x02828 + ((
_n) *
0x100)) : (
0x0C028 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x03800 + ((
_n) *
0x100)) : (
0x0E000 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x03804 + ((
_n) *
0x100)) : (
0x0E004 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x03808 + ((
_n) *
0x100)) : (
0x0E008 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x03810 + ((
_n) *
0x100)) : (
0x0E010 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x03818 + ((
_n) *
0x100)) : (
0x0E018 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x03828 + ((
_n) *
0x100)) : (
0x0E028 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x03838 + ((
_n) *
0x100)) : (
0x0E038 + ((
_n) *
0x40)))
((
_n) <
4 ? (
0x0383C + ((
_n) *
0x100)) : (
0x0E03C + ((
_n) *
0x40)))
#
define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */#
define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */#
define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ (((
_i) <=
15) ? (
0x05400 + ((
_i) *
8)) : (
0x054E0 + ((
_i -
16) *
8)))
(((
_i) <=
15) ? (
0x05404 + ((
_i) *
8)) : (
0x054E4 + ((
_i -
16) *
8)))
#
define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */#
define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */#
define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */#
define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */#
define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */#
define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */#
define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */#
define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */#
define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */#
define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */#
define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */#
define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */#
define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */#
define E1000_IAC 0x04100 /* Interrupt Assertion Count *//* Interrupt Cause Rx Pkt Timer Expire Count */
/* Interrupt Cause Rx Abs Timer Expire Count */
/* Interrupt Cause Tx Pkt Timer Expire Count */
/* Interrupt Cause Tx Abs Timer Expire Count */
/* Interrupt Cause Tx Queue Empty Count */
/* Interrupt Cause Tx Queue Min Thresh Count */
/* Interrupt Cause Rx Desc Min Thresh Count */
/* Interrupt Cause Receiver Overrun Count */
#
define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */#
define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */#
define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */#
define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */#
define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */#
define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */#
define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */#
define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */#
define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */#
define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */#
define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */#
define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */#
define E1000_RFCTL 0x05008 /* Receive Filter Control */#
define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */#
define E1000_RA 0x05400 /* Receive Address - RW Array */#
define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */#
define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */#
define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */#
define E1000_WUC 0x05800 /* Wakeup Control - RW */#
define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */#
define E1000_WUS 0x05810 /* Wakeup Status - RO */#
define E1000_MANC 0x05820 /* Management Control - RW */#
define E1000_IPAV 0x05838 /* IP Address Valid - RW */#
define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */#
define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */#
define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */#
define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */#
define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */#
define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */#
define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
#
define E1000_MANC2H 0x05860 /* Management Control To Host - RW */#
define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */#
define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */#
define E1000_GCR 0x05B00 /* PCI-Ex Control */#
define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */#
define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */#
define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */#
define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */#
define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */#
define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */#
define E1000_HICR 0x08F00 /* Host Interface Control */
/* RSS registers */
#
define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */#
define E1000_IMIR(
_i) (
0x05A80 + ((
_i) *
4))
/* Immediate Interrupt */#
define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW *//* MSI-X Allocation Register (_i) - RW */
/* MSI-X Table entry addr low reg - RW */
/* MSI-X Table entry addr upper reg - RW */
/* MSI-X Table entry message reg - RW */
/* MSI-X Table entry vector ctrl reg - RW */
#
define E1000_RETA(
_i) (
0x05C00 + ((
_i) *
4))
/* Redirection Table - RW */#
define E1000_RSSIR 0x05868 /* RSS Interrupt Request */#
define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */#
define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */
}
#endif
#endif /* _E1000_REGS_H_ */