/*
* This file is provided under a CDDLv1 license. When using or
* redistributing this file, you may do so under this license.
* In redistributing this file this license must be included
* and no other modification of this header file is permitted.
*
* CDDL LICENSE SUMMARY
*
* Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved.
*
* The contents of this file are subject to the terms of Version
* 1.0 of the Common Development and Distribution License (the "License").
*
* You should have received a copy of the License with this software.
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDLv1.
*/
/*
* IntelVersion: HSD_2343720b_DragonLake3 v2007-06-14_HSD_2343720b_DragonLake3
*/
#pragma ident "%Z%%M% %I% %E% SMI"
extern "C" {
#endif
#
define E1000_CTRL 0x00000 /* Device Control - RW */#
define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */#
define E1000_FLA 0x0001C /* Flash Access - RW */#
define E1000_SCTL 0x00024 /* SerDes Control - RW */#
define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */#
define E1000_FCAH 0x0002C /* Flow Control Address High -RW */#
define E1000_FCT 0x00030 /* Flow Control Type - RW */#
define E1000_VET 0x00038 /* VLAN Ether Type - RW */#
define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */#
define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */#
define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */#
define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */#
define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */#
define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */#
define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */#
define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */#
define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */#
define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */#
define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */#
define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */#
define E1000_TXCW 0x00178 /* TX Configuration Word - RW */#
define E1000_RXCW 0x00180 /* RX Configuration Word - RO */#
define E1000_EITR0 0x01680 /* Ext. Int. Throttling Rate Vector 0 - RW */#
define E1000_EITR1 0x01684 /* Ext. Int. Throttling Rate Vector 1 - RW */#
define E1000_EITR2 0x01688 /* Ext. Int. Throttling Rate Vector 2 - RW */#
define E1000_EITR3 0x0168C /* Ext. Int. Throttling Rate Vector 3 - RW */#
define E1000_EITR4 0x01690 /* Ext. Int. Throttling Rate Vector 4 - RW */#
define E1000_EITR5 0x01694 /* Ext. Int. Throttling Rate Vector 5 - RW */#
define E1000_EITR6 0x01698 /* Ext. Int. Throttling Rate Vector 6 - RW */#
define E1000_EITR7 0x0169C /* Ext. Int. Throttling Rate Vector 7 - RW */#
define E1000_EITR8 0x016A0 /* Ext. Int. Throttling Rate Vector 8 - RW */#
define E1000_EITR9 0x016A4 /* Ext. Int. Throttling Rate Vector 9 - RW */#
define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */#
define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */#
define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */#
define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */#
define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */#
define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */#
define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */#
define E1000_TBT 0x00448 /* TX Burst Timer - RW */#
define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */#
define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */#
define E1000_PBS 0x01008 /* Packet Buffer Size */#
define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */#
define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */#
define E1000_FLOP 0x0103C /* FLASH Opcode Register */#
define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */#
define E1000_ICR_V2 0x01500 /* Interrupt Cause - new location - RC */#
define E1000_ICS_V2 0x01504 /* Interrupt Cause Set - new location - WO */#
define E1000_IMC_V2 0x0150C /* Interrupt Mask Clear - new location - WO */#
define E1000_IAM_V2 0x01510 /* Interrupt Ack Auto Mask -new location -RW */#
define E1000_ERT 0x02008 /* Early Rx Threshold - RW */#
define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */#
define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */#
define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */#
define E1000_PBRTH 0x02458 /* PB RX Arbitration Threshold - RW */#
define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW *//* Split and Replication RX Control - RW */
#
define E1000_RDPUMB 0x025CC /* DMA RX Descriptor uC Mailbox - RW */#
define E1000_RDPUAD 0x025D0 /* DMA RX Descriptor uC Addr Command - RW */#
define E1000_RDPUWD 0x025D4 /* DMA RX Descriptor uC Data Write - RW */#
define E1000_RDPURD 0x025D8 /* DMA RX Descriptor uC Data Read - RW */#
define E1000_RDPUCTL 0x025DC /* DMA RX Descriptor uC Control - RW */#
define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */#
define E1000_RXPBS 0x02404 /* RX Packet Buffer Size - RW */#
define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */#
define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */#
define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */#
define E1000_RDH 0x02810 /* RX Descriptor Head - RW */#
define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */#
define E1000_RDTR 0x02820 /* RX Delay Timer - RW */#
define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */#
define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */#
define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW *//*
* Convenience macros
*
* Note: "_n" is the queue number of the register to be written to.
*
* Example usage:
* E1000_RDBAL_REG(current_rx_queue)
*/
#
define E1000_RDBAL2 0x02A00 /* RX Descriptor Base Low Queue 2 - RW */#
define E1000_RDBAH2 0x02A04 /* RX Descriptor Base High Queue 2 - RW */#
define E1000_RDLEN2 0x02A08 /* RX Descriptor Length Queue 2 - RW */#
define E1000_RDH2 0x02A10 /* RX Descriptor Head Queue 2 - RW */#
define E1000_RDT2 0x02A18 /* RX Descriptor Tail Queue 2 - RW */#
define E1000_RXDCTL2 0x02A28 /* RX Descriptor Control queue 2 - RW */#
define E1000_RDBAL3 0x02B00 /* RX Descriptor Base Low Queue 3 - RW */#
define E1000_RDBAH3 0x02B04 /* RX Descriptor Base High Queue 3 - RW */#
define E1000_RDLEN3 0x02B08 /* RX Descriptor Length Queue 3 - RW */#
define E1000_RDH3 0x02B10 /* RX Descriptor Head Queue 3 - RW */#
define E1000_RDT3 0x02B18 /* RX Descriptor Tail Queue 3 - RW */#
define E1000_RXDCTL3 0x02B28 /* RX Descriptor Control Queue 3 - RW */#
define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */#
define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */#
define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */#
define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */#
define E1000_TXPBS 0x03404 /* TX Packet Buffer Size - RW */#
define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */#
define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */#
define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */#
define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */#
define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */#
define E1000_TDPUMB 0x0357C /* DMA TX Descriptor uC Mail Box - RW */#
define E1000_TDPUAD 0x03580 /* DMA TX Descriptor uC Addr Command - RW */#
define E1000_TDPUWD 0x03584 /* DMA TX Descriptor uC Data Write - RW */#
define E1000_TDPURD 0x03588 /* DMA TX Descriptor uC Data Read - RW */#
define E1000_TDPUCTL 0x0358C /* DMA TX Descriptor uC Control - RW */#
define E1000_DTXMXSZRQ 0x03540 /* DMA TX Max Total Allow Size Requests - RW */#
define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */#
define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */#
define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */#
define E1000_TDH 0x03810 /* TX Descriptor Head - RW */#
define E1000_TDT 0x03818 /* TX Descriptor Tail - RW */#
define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */#
define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */#
define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */#
define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */#
define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */#
define E1000_TDWBAL0 0x03838 /* TX Desc. WB Addr Low Queue 0 - RW */#
define E1000_TDWBAH0 0x0383C /* TX Desc. WB Addr High Queue 0 - RW */#
define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */#
define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */#
define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */#
define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */#
define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */#
define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */#
define E1000_TDWBAL1 0x03938 /* TX Descriptor WB Addr Low Queue 1 - RW */#
define E1000_TDWBAH1 0x0393C /* TX Descriptor WB Addr High Queue 1 - RW */#
define E1000_TDBAL2 0x03A00 /* TX Descriptor Base Low Queue 2 - RW */#
define E1000_TDBAH2 0x03A04 /* TX Descriptor Base High Queue 2 - RW */#
define E1000_TDLEN2 0x03A08 /* TX Descriptor Length Queue 2 - RW */#
define E1000_TDH2 0x03A10 /* TX Descriptor Head Queue 2 - RW */#
define E1000_TDT2 0x03A18 /* TX Descriptor Tail Queue 2 - RW */#
define E1000_TDWBAL2 0x03A38 /* TX Descriptor WB Addr Low Queue 2 - RW */#
define E1000_TDWBAH2 0x03A3C /* TX Descriptor WB Addr High Queue 2 - RW */#
define E1000_TDBAL3 0x03B00 /* TX Descriptor Base Low Queue 3 - RW */#
define E1000_TDBAH3 0x03B04 /* TX Descriptor Base High Queue 3 - RW */#
define E1000_TDLEN3 0x03B08 /* TX Descriptor Length Queue 3 - RW */#
define E1000_TDH3 0x03B10 /* TX Descriptor Head Queue 3 - RW */#
define E1000_TDT3 0x03B18 /* TX Descriptor Tail Queue 3 - RW */#
define E1000_TDWBAL3 0x03B38 /* TX Descriptor WB Addr Low Queue 3 - RW */#
define E1000_TDWBAH3 0x03B3C /* TX Descriptor WB Addr High Queue 3 - RW */#
define E1000_IAC 0x04100 /* Interrupt Assertion Count *//* Interrupt Cause Rx Packet Timer Expire Count */
/* Interrupt Cause Rx Absolute Timer Expire Count */
/* Interrupt Cause Tx Packet Timer Expire Count */
/* Interrupt Cause Tx Absolute Timer Expire Count */
/* Interrupt Cause Tx Queue Empty Count */
/* Interrupt Cause Tx Queue Minimum Threshold Count */
/* Interrupt Cause Rx Descriptor Minimum Threshold Count */
/* Interrupt Cause Receiver Overrun Count */
/* Switch Security Violation Packet Count */
/* LinkSec TX Untagged Packet Count */
/* LinkSec Encrypted TX Packets Count */
/* LinkSec Protected TX Packet Count */
/* LinkSec Encrypted TX Octets Count */
/* LinkSec Protected TX Octets Count */
/* LinkSec Untagged non-Strict RX Packet Count */
/* LinkSec Untagged Strict RX Packet Count */
/* LinkSec RX Octets Decrypted Count */
/* LinkSec RX Octets Validated */
/* LinkSec RX Bad Tag */
/* LinkSec non-Strict RX Packet Unknown SCI Count */
/* LinkSec Strict RX Packet Unknown SCI Count */
/* LinkSec RX Unchecked Packets Count */
/* LinkSec RX Delayed Packet Count */
/* LinkSec RX Late Packets Count */
/* LinkSec TX Capabilities Register - RO */
/* LinkSec RX Capabilities Register - RO */
/* LinkSec TX Control - RW */
/* LinkSec RX Control - RW */
/* LinkSec TX SCI Low - RW */
/* LinkSec TX SCI High - RW */
/* LinkSec TX SA0 - RW */
/* LinkSec TX SA PN 0 - RW */
/* LinkSec TX SA PN 1 - RW */
/* LinkSec RX SCI Low - RW */
/* LinkSec RX SCI High - RW */
/* LinkSec TX 128-bit Key 0 - WO */
/* LinkSec TX 128-bit Key 1 - WO */
/* LinkSec RX SAs - RW */
/* LinkSec RX SAs - RW */
/*
* LinkSec RX Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
* key - RW.
*/
/* IPSec RX IPv4/v6 Address - RW */ /* IPSec RX 128-bit Key - RW */
/* IPSec TX 128-bit Key - RW */
#
define E1000_CBTMPC 0x0402C /* Circuit Breaker TX Packet Count */#
define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */#
define E1000_CBRDPC 0x04044 /* Circuit Breaker RX Dropped Count */#
define E1000_CBRMPC 0x040FC /* Circuit Breaker RX Packet Count */#
define E1000_HGPTC 0x04118 /* Host Good Packets TX Count */#
define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */#
define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */#
define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */#
define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */#
define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */#
define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */#
define E1000_RLPML 0x05004 /* RX Long Packet Max Length */#
define E1000_RFCTL 0x05008 /* Receive Filter Control */#
define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */#
define E1000_RA 0x05400 /* Receive Address - RW Array */#
define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW */#
define E1000_PSRTYPE 0x05480 /* Packet Split Receive Type - RW */#
define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */#
define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */#
define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */#
define E1000_WUC 0x05800 /* Wakeup Control - RW */#
define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */#
define E1000_WUS 0x05810 /* Wakeup Status - RO */#
define E1000_MANC 0x05820 /* Management Control - RW */#
define E1000_IPAV 0x05838 /* IP Address Valid - RW */#
define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */#
define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */#
define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */#
define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */#
define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */#
define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */#
define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
#
define E1000_MANC2H 0x05860 /* Management Control To Host - RW */#
define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */#
define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */#
define E1000_GCR 0x05B00 /* PCI-Ex Control */#
define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */#
define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */#
define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */#
define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */#
define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */#
define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */#
define E1000_HICR 0x08F00 /* Host Inteface Control */
/* RSS registers */
#
define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */#
define E1000_IMIR(
_i) (
0x05A80 + ((
_i) *
4))
/* Immediate Interrupt */#
define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */#
define E1000_MSIXBM0 0x01600 /* MSI-X Allocation Register 0 - RW */#
define E1000_MSIXBM1 0x01604 /* MSI-X Allocation Register 1 - RW */#
define E1000_MSIXBM2 0x01608 /* MSI-X Allocation Register 2 - RW */#
define E1000_MSIXBM3 0x0160C /* MSI-X Allocation Register 3 - RW */#
define E1000_MSIXBM4 0x01610 /* MSI-X Allocation Register 4 - RW */#
define E1000_MSIXBM5 0x01614 /* MSI-X Allocation Register 5 - RW */#
define E1000_MSIXBM6 0x01618 /* MSI-X Allocation Register 6 - RW */#
define E1000_MSIXBM7 0x0161C /* MSI-X Allocation Register 7 - RW */#
define E1000_MSIXBM8 0x01620 /* MSI-X Allocation Register 8 - RW */#
define E1000_MSIXBM9 0x01624 /* MSI-X Allocation Register 9 - RW */#
define E1000_MSIXTADD0 0x0C000 /* MSI-X Table entry addr low reg 0 - RW */#
define E1000_MSIXTADD1 0x0C010 /* MSI-X Table entry addr low reg 1 - RW */#
define E1000_MSIXTADD2 0x0C020 /* MSI-X Table entry addr low reg 2 - RW */#
define E1000_MSIXTADD3 0x0C030 /* MSI-X Table entry addr low reg 3 - RW */#
define E1000_MSIXTADD4 0x0C040 /* MSI-X Table entry addr low reg 4 - RW */#
define E1000_MSIXTADD5 0x0C050 /* MSI-X Table entry addr low reg 5 - RW */#
define E1000_MSIXTADD6 0x0C060 /* MSI-X Table entry addr low reg 6 - RW */#
define E1000_MSIXTADD7 0x0C070 /* MSI-X Table entry addr low reg 7 - RW */#
define E1000_MSIXTADD8 0x0C080 /* MSI-X Table entry addr low reg 8 - RW */#
define E1000_MSIXTADD9 0x0C090 /* MSI-X Table entry addr low reg 9 - RW */#
define E1000_RETA 0x05C00 /* Redirection Table - RW Array */#
define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */#
define E1000_RSSIR 0x05868 /* RSS Interrupt Request *//* VT Registers */
#
define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */#
define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */#
define E1000_VFRE 0x00C8C /* VF Receive Enables */#
define E1000_VFTE 0x00C90 /* VF Transmit Enables */#
define E1000_QDE 0x02408 /* Queue Drop Enable - RW */#
define E1000_DTXSWC 0x03500 /* DMA TX Switch Control - RW */#
define E1000_VLVF 0x05D00 /* VLAN Virtual Machine Filter - RW */#
define E1000_UTA 0x0A000 /* Unicast Table Array - RW *//* These act per VF so an array friendly macro is used */
/* Time Sync */
#
define E1000_RXSATRL 0x0B62C /* RX timestamp attribute low - RO */#
define E1000_RXSATRH 0x0B630 /* RX timestamp attribute high - RO */#
define E1000_SYSTIML 0x0B600 /* System time register Low - RO */#
define E1000_SYSTIMH 0x0B604 /* System time register High - RO */#
define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */
/* Filtering Registers */
#
define E1000_SAQF(
_n) (
0x05980 + (
4 * (
_n)))
/* Source Address Queue Fltr */#
define E1000_DAQF(
_n) (
0x059A0 + (
4 * (
_n)))
/* Dest Address Queue Fltr */#
define E1000_SPQF(
_n) (
0x059C0 + (
4 * (
_n)))
/* Source Port Queue Fltr */#
define E1000_FTQF(
_n) (
0x059E0 + (
4 * (
_n)))
/* 5-tuple Queue Fltr */
#
define E1000_RTTDCS 0x3600 /* Reedtown TX Desc plane control and status */#
define E1000_RTTPCS 0x3474 /* Reedtown TX Packet Plane control and status */#
define E1000_RTRPCS 0x2474 /* RX packet plane control and status */#
define E1000_RTRUP2TC 0x05AC4 /* RX User Priority to Traffic Class */#
define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class *//* Tx Desc plane TC Rate-scheduler config */
/* Tx Packet plane TC Rate-Scheduler Config */
/* Rx Packet plane TC Rate-Scheduler Config */
/* Tx Desc Plane TC Rate-Scheduler Status */
/* Tx Desc Plane TC Rate-Scheduler MMW */
/* Tx Packet plane TC Rate-Scheduler Status */
/* Tx Packet plane TC Rate-scheduler MMW */
/* Rx Packet plane TC Rate-Scheduler Status */
/* Rx Packet plane TC Rate-Scheduler MMW */
/* Tx Desc plane VM Rate-Scheduler MMW */
/* Tx BCN Rate-Scheduler MMW */
#
define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */#
define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */#
define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */
}
#endif
#endif /* _E1000_REGS_H_ */