e1000_osdep.c revision 25f2d433de915875c8393f0b0dc14aa155997ad0
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/*
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * This file is provided under a CDDLv1 license. When using or
3e14f97f673e8a630f076077de35afdd43dc1587Roger A. Faulkner * redistributing this file, you may do so under this license.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * In redistributing this file this license must be included
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * and no other modification of this header file is permitted.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * CDDL LICENSE SUMMARY
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * The contents of this file are subject to the terms of Version
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * 1.0 of the Common Development and Distribution License (the "License").
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * You should have received a copy of the License with this software.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * You can obtain a copy of the License at
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * http://www.opensolaris.org/os/licensing.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * See the License for the specific language governing permissions
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * and limitations under the License.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/*
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Use is subject to license terms of the CDDLv1.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#pragma ident "%Z%%M% %I% %E% SMI"
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#include "e1000_osdep.h"
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin#include "e1000_api.h"
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chins32
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chine1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin hw->dev_spec = kmem_zalloc(size, KM_SLEEP);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin return (E1000_SUCCESS);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinvoid
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chine1000_free_dev_spec_struct(struct e1000_hw *hw)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin if (hw->dev_spec == NULL)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin return;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin kmem_free(hw->dev_spec, hw->dev_spec_size);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin hw->dev_spec = NULL;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinvoid
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chine1000_pci_set_mwi(struct e1000_hw *hw)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin uint16_t val = hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinvoid
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chine1000_pci_clear_mwi(struct e1000_hw *hw)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin uint16_t val = hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinvoid
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chine1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinvoid
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chine1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *value =
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin pci_config_get16(OS_DEP(hw)->cfg_handle, reg);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/*
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * phy_spd_state - set smart-power-down (SPD) state
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * This only acts on the 82541/47 family and the 82571/72 family.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * For any others, return without doing anything.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinvoid
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinphy_spd_state(struct e1000_hw *hw, boolean_t enable)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin int32_t offset; /* offset to register */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin uint16_t spd_bit; /* bit to be set */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin uint16_t reg; /* register contents */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin switch (hw->mac.type) {
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin case e1000_82541:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin case e1000_82547:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin case e1000_82541_rev_2:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin case e1000_82547_rev_2:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin offset = IGP01E1000_GMII_FIFO;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin spd_bit = IGP01E1000_GMII_SPD;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin break;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin case e1000_82571:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin case e1000_82572:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin offset = IGP02E1000_PHY_POWER_MGMT;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin spd_bit = IGP02E1000_PM_SPD;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin break;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin default:
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin return; /* no action */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin }
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin e1000_read_phy_reg(hw, offset, &reg);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin if (enable)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin reg |= spd_bit; /* enable: set the spd bit */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin else
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin reg &= ~spd_bit; /* disable: clear the spd bit */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin e1000_write_phy_reg(hw, offset, reg);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/*
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * The real intent of this routine is to return the value from pci-e
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * config space at offset reg into the capability space.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * ICH devices are "PCI Express"-ish. They have a configuration space,
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * but do not contain PCI Express Capability registers, so this returns
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin * the equivalent of "not supported"
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin */
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chinint32_t
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chine1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin{
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin *value = pci_config_get16(OS_DEP(hw)->cfg_handle,
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin PCI_EX_CONF_CAP + reg);
7c2fbfb345896881c631598ee3852ce9ce33fb07April Chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin return (0);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin/*
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * Enables PCI-Express master access.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * hw: Struct containing variables accessed by shared code
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin *
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin * returns: - none.
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin */
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chinvoid
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chine1000_enable_pciex_master(struct e1000_hw *hw)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin{
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin uint32_t ctrl;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin if (hw->bus.type != e1000_bus_type_pci_express)
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin return;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin ctrl = E1000_READ_REG(hw, E1000_CTRL);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin}
da2e3ebdc1edfbc5028edf1354e7dd2fa69a7968chin