e1000_ich8lan.h revision 4d7379630d53d9992780329b674af8c85935e858
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * This file is provided under a CDDLv1 license. When using or
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * redistributing this file, you may do so under this license.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * In redistributing this file this license must be included
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * and no other modification of this header file is permitted.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * CDDL LICENSE SUMMARY
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * The contents of this file are subject to the terms of Version
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * 1.0 of the Common Development and Distribution License (the "License").
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * You should have received a copy of the License with this software.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * You can obtain a copy of the License at
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * See the License for the specific language governing permissions
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * and limitations under the License.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Use is subject to license terms of the CDDLv1.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * IntelVersion: 1.23 v2008-7-17_MountAngel2
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/* FW established a valid mode */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Additional interrupts need to be handled for ICH family:
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * DSW = The FW changed the status of the DISSW bit in FWSM
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * PHYINT = The LAN connected device generates an interrupt
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * EPRST = Manageability reset event
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/* Additional interrupt register bit definitions */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/* Security Processing bit Indication */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchivoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchivoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchivoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchivoid e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#endif /* _E1000_ICH8LAN_H_ */