e1000_82543.c revision caf05df5c10c960028f122b1b02a3f7d8f892c31
/*
* This file is provided under a CDDLv1 license. When using or
* redistributing this file, you may do so under this license.
* In redistributing this file this license must be included
* and no other modification of this header file is permitted.
*
* CDDL LICENSE SUMMARY
*
* Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
*
* The contents of this file are subject to the terms of Version
* 1.0 of the Common Development and Distribution License (the "License").
*
* You should have received a copy of the License with this software.
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDLv1.
*/
/*
* IntelVersion: 1.68 v3-1-3_2009-8-20
*/
/*
* 82543GC Gigabit Ethernet Controller (Fiber)
* 82543GC Gigabit Ethernet Controller (Copper)
* 82544EI Gigabit Ethernet Controller (Copper)
* 82544EI Gigabit Ethernet Controller (Fiber)
* 82544GC Gigabit Ethernet Controller (Copper)
* 82544GC Gigabit Ethernet Controller (LOM)
*/
#include "e1000_api.h"
/*
* e1000_init_phy_params_82543 - Init PHY func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_phy_params_82543");
goto out;
} else {
}
/* Function Pointers */
/*
* The external PHY of the 82543 can be in a funky state.
* Resetting helps us read the PHY registers for acquiring
* the PHY ID.
*/
if (!e1000_init_phy_disabled_82543(hw)) {
if (ret_val) {
DEBUGOUT("Resetting PHY during init failed.\n");
goto out;
}
msec_delay(20);
}
if (ret_val)
goto out;
/* Verify phy id */
case e1000_82543:
ret_val = -E1000_ERR_PHY;
goto out;
}
break;
case e1000_82544:
ret_val = -E1000_ERR_PHY;
goto out;
}
break;
default:
ret_val = -E1000_ERR_PHY;
goto out;
}
out:
return (ret_val);
}
/*
* e1000_init_nvm_params_82543 - Init NVM func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_nvm_params_82543");
/* Function Pointers */
return (E1000_SUCCESS);
}
/*
* e1000_init_mac_params_82543 - Init MAC func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_mac_params_82543");
/* Set media type */
break;
default:
break;
}
/* Set mta register count */
/* Set rar entry count */
/* Function pointers */
/* function id */
/* reset */
/* hw initialization */
/* link setup */
/* physical interface setup */
/* check for link */
/* link info */
/* multicast address update */
/* writing VFTA */
/* clearing VFTA */
/* setting MTA */
/* clear hardware counters */
/* Set tbi compatibility */
e1000_set_tbi_compatibility_82543(hw, false);
return (E1000_SUCCESS);
}
/*
* e1000_init_function_pointers_82543 - Init func ptrs.
* @hw: pointer to the HW structure
*
* Called to initialize all function pointers and parameters.
*/
void
{
DEBUGFUNC("e1000_init_function_pointers_82543");
}
/*
* e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
* @hw: pointer to the HW structure
*
* Returns the current status of 10-bit Interface (TBI) compatibility
*/
static bool
{
bool state = false;
DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
goto out;
}
? true : false;
out:
return (state);
}
/*
* e1000_set_tbi_compatibility_82543 - Set TBI compatibility
* @hw: pointer to the HW structure
*
* Enables or disabled 10-bit Interface (TBI) compatibility.
*/
void
{
DEBUGFUNC("e1000_set_tbi_compatibility_82543");
DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
return;
}
if (state)
else
}
/*
* e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
* @hw: pointer to the HW structure
*
* Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
*/
bool
{
bool state = false;
DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
goto out;
}
? true : false;
out:
return (state);
}
/*
* e1000_set_tbi_sbp_82543 - Set TBI SBP
* @hw: pointer to the HW structure
*
* Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
*/
static void
{
DEBUGFUNC("e1000_set_tbi_sbp_82543");
else
}
/*
* e1000_init_phy_disabled_82543 - Returns init PHY status
* @hw: pointer to the HW structure
*
* Returns the current status of whether PHY initialization is disabled.
* True if PHY initialization is disabled else false.
*/
static bool
{
bool ret_val;
DEBUGFUNC("e1000_init_phy_disabled_82543");
ret_val = false;
goto out;
}
out:
return (ret_val);
}
/*
* e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
* @hw: pointer to the HW structure
* @stats: Struct containing statistic register values
* @frame_len: The length of the frame in question
* @mac_addr: The Ethernet destination address of the frame in question
* @max_frame_size: The maximum frame size
*
* Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
*/
void
{
if (!(e1000_tbi_sbp_enabled_82543(hw)))
return;
/* First adjust the frame length. */
frame_len--;
/*
* We need to adjust the statistics counters, since the hardware
* counters overcount this packet as a CRC error and undercount
* the packet as a good packet
*/
/* This packet should not be counted as a CRC error. */
/* This packet does count as a Good Packet Received. */
/* Adjust the Good Octets received counters */
/*
* Is this a broadcast or multicast? Check broadcast first, since
* the test for a multicast frame will test positive on a broadcast
* frame.
*/
/* Broadcast packet */
else if (*mac_addr & 0x01)
/* Multicast packet */
/*
* In this case, the hardware has overcounted the number of
* oversize frames.
*/
/*
* Adjust the bin counters when the extra byte put the frame in the
* wrong bin. Remember that the frame_len was adjusted above.
*/
if (frame_len == 64) {
} else if (frame_len == 127) {
} else if (frame_len == 255) {
} else if (frame_len == 511) {
} else if (frame_len == 1023) {
} else if (frame_len == 1522) {
}
}
/*
* e1000_read_phy_reg_82543 - Read PHY register
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* Reads the PHY at offset and stores the information read to data.
*/
static s32
{
DEBUGFUNC("e1000_read_phy_reg_82543");
if (offset > MAX_PHY_REG_ADDRESS) {
goto out;
}
/*
* We must first send a preamble through the MDIO pin to signal the
* beginning of an MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
/*
* Now combine the next few fields that are required for a read
* operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine five different times. The format
* of an MII read instruction consists of a shift out of 14 bits and
* is defined as follows:
* <Preamble><SOF><Op Code><Phy Addr><Offset>
* followed by a shift in of 18 bits. This first two bits shifted in
* are TurnAround bits used to avoid contention on the MDIO pin when a
* READ operation is performed. These two bits are thrown away
* followed by a shift in of 16 bits which contains the desired data.
*/
/*
* Now that we've shifted out the read command to the MII, we need to
* "shift in" the 16-bit value (18 total bits) of the requested PHY
* register address.
*/
out:
return (ret_val);
}
/*
* e1000_write_phy_reg_82543 - Write PHY register
* @hw: pointer to the HW structure
* @offset: register offset to be written
* @data: pointer to the data to be written at offset
*
* Writes data to the PHY at offset.
*/
static s32
{
DEBUGFUNC("e1000_write_phy_reg_82543");
if (offset > MAX_PHY_REG_ADDRESS) {
goto out;
}
/*
* We'll need to use the SW defined pins to shift the write command
* out to the PHY. We first send a preamble to the PHY to signal the
* beginning of the MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
/*
* Now combine the remaining required fields that will indicate a
* write operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine for each field in the command. The
* format of a MII write instruction is as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
mdic <<= 16;
out:
return (ret_val);
}
/*
* e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
* @hw: pointer to the HW structure
* @ctrl: pointer to the control register
*
* Raise the management data input clock by setting the MDC bit in the control
* register.
*/
static void
{
/*
* Raise the clock input to the Management Data Clock (by setting the
* MDC bit), and then delay a sufficient amount of time.
*/
usec_delay(10);
}
/*
* e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
* @hw: pointer to the HW structure
* @ctrl: pointer to the control register
*
* Lower the management data input clock by clearing the MDC bit in the control
* register.
*/
static void
{
/*
* Lower the clock input to the Management Data Clock (by clearing the
* MDC bit), and then delay a sufficient amount of time.
*/
usec_delay(10);
}
/*
* e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
* @hw: pointer to the HW structure
* @data: data to send to the PHY
* @count: number of bits to shift out
*
* We need to shift 'count' bits out to the PHY. So, the value in the
* "data" parameter will be shifted out to the PHY one bit at a time.
* In order to do this, "data" must be broken down into bits.
*/
static void
{
/*
* We need to shift "count" number of bits out to the PHY. So, the
* value in the "data" parameter will be shifted out to the PHY one
* bit at a time. In order to do this, "data" must be broken down
* into bits.
*/
mask = 0x01;
/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
while (mask) {
/*
* A "1" is shifted out to the PHY by setting the MDIO bit to
* "1" and then raising and lowering the Management Data Clock.
* A "0" is shifted out to the PHY by setting the MDIO bit to
* "0" and then raising and lowering the clock.
*/
ctrl |= E1000_CTRL_MDIO;
else
ctrl &= ~E1000_CTRL_MDIO;
usec_delay(10);
mask >>= 1;
}
}
/*
* e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
* @hw: pointer to the HW structure
*
* In order to read a register from the PHY, we need to shift 18 bits
* in from the PHY. Bits are "shifted in" by raising the clock input to
* the PHY (setting the MDC bit), and then reading the value of the data out
* MDIO bit.
*/
static u16
{
u8 i;
/*
* In order to read a register from the PHY, we need to shift in a
* total of 18 bits from the PHY. The first two bit (turnaround)
* times are used to avoid contention on the MDIO pin when a read
* operation is performed. These two bits are ignored by us and
* thrown away. Bits are "shifted in" by raising the input to the
* Management Data Clock (setting the MDC bit) and then reading the
* value of the MDIO bit.
*/
/*
* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
* input.
*/
ctrl &= ~E1000_CTRL_MDIO_DIR;
ctrl &= ~E1000_CTRL_MDIO;
/*
* Raise and lower the clock before reading in the data. This accounts
* for the turnaround bits. The first clock occurred when we clocked
* out the last bit of the Register Address.
*/
for (data = 0, i = 0; i < 16; i++) {
data <<= 1;
/* Check to see if we shifted in a "1". */
if (ctrl & E1000_CTRL_MDIO)
data |= 1;
}
return (data);
}
/*
* @hw: pointer to the HW structure
*
* Calls the function to force speed and duplex for the m88 PHY, and
* if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
* then call the function for polarity reversal workaround.
*/
static s32
{
DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
* @hw: pointer to the HW structure
*
* When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
* inadvertently. To workaround the issue, we disable the transmitter on
* the PHY until we have established the link partner's link parameters.
*/
static s32
{
u16 i;
bool link;
goto out;
/* Polarity reversal workaround for forced 10F/10H links. */
/* Disable the transmitter on the PHY */
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
/*
* This loop will early-out if the NO link condition has been met.
* In other words, DO NOT use e1000_phy_has_link_generic() here.
*/
for (i = PHY_FORCE_TIME; i > 0; i--) {
/*
* Read the MII Status Register and wait for Link Status bit
* to be clear.
*/
if (ret_val)
goto out;
if (ret_val)
goto out;
if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
break;
msec_delay_irq(100);
}
/* Recommended delay time after link has been lost */
msec_delay_irq(1000);
/* Now we will re-enable the transmitter on the PHY */
if (ret_val)
goto out;
msec_delay_irq(50);
if (ret_val)
goto out;
msec_delay_irq(50);
if (ret_val)
goto out;
msec_delay_irq(50);
if (ret_val)
goto out;
if (ret_val)
goto out;
/*
* Read the MII Status Register and wait for Link Status bit
* to be set.
*/
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* e1000_phy_hw_reset_82543 - PHY hardware reset
* @hw: pointer to the HW structure
*
* Sets the PHY_RESET_DIR bit in the extended device control register
* to put the PHY into a reset and waits for completion. Once the reset
* has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
* of reset.
*/
static s32
{
DEBUGFUNC("e1000_phy_hw_reset_82543");
/*
* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset...
*/
msec_delay(10);
/* ...then take it out of reset. */
usec_delay(150);
return (E1000_SUCCESS);
return (ret_val);
}
/*
* e1000_reset_hw_82543 - Reset hardware
* @hw: pointer to the HW structure
*
* This resets the hardware into a known state.
*/
static s32
{
DEBUGFUNC("e1000_reset_hw_82543");
DEBUGOUT("Masking off all interrupts\n");
e1000_set_tbi_sbp_82543(hw, false);
/*
* Delay to allow any outstanding PCI transactions to complete before
* resetting the device
*/
msec_delay(10);
DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
} else {
/*
* The 82544 can't ACK the 64-bit write when issuing the
* reset, so use IO-mapping as a workaround.
*/
}
/*
* After MAC reset, force reload of NVM to restore power-on
* settings to device.
*/
msec_delay(2);
/* Masking off and clearing any pending interrupts */
return (ret_val);
}
/*
* e1000_init_hw_82543 - Initialize hardware
* @hw: pointer to the HW structure
*
* This inits the hardware readying it for operation.
*/
static s32
{
u16 i;
DEBUGFUNC("e1000_init_hw_82543");
/* Disabling VLAN filtering */
/* Setup the receive address. */
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++) {
}
/*
* Set the PCI priority bit correctly in the CTRL register. This
* determines if the adapter gives priority to receives, or if it
* gives equal priority to transmits and receives.
*/
}
/* Setup link and flow control */
/*
* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
*/
return (ret_val);
}
/*
* e1000_setup_link_82543 - Setup flow control and link settings
* @hw: pointer to the HW structure
*
* Read the EEPROM to determine the initial polarity value and write the
* extended device control register with the information before calling
* the generic setup link function, which does the following:
* Determines which flow control settings to use, then configures flow
* control. Calls the appropriate media-specific link configuration
* function. Assuming the adapter has a valid link partner, a valid link
* should be established. Assumes the hardware has previously been reset
* and the transmitter and receiver are not enabled.
*/
static s32
{
DEBUGFUNC("e1000_setup_link_82543");
/*
* Take the 4 bits from NVM word 0xF that determine the initial
* polarity value for the SW controlled pins, and setup the
* Extended Device Control reg with that info.
* This is needed because one of the SW controlled pins is used for
* signal detection. So this should be done before phy setup.
*/
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
ret_val = -E1000_ERR_NVM;
goto out;
}
}
out:
return (ret_val);
}
/*
* e1000_setup_copper_link_82543 - Configure copper link settings
* @hw: pointer to the HW structure
*
* Configures the link for auto-neg or forced speed and duplex. Then we check
* for link, once link is established calls to configure collision distance
* and flow control are called.
*/
static s32
{
bool link;
DEBUGFUNC("e1000_setup_copper_link_82543");
/*
* With 82543, we need to force speed and duplex on the MAC
* equal to what the PHY speed and duplex configuration is.
* In addition, we need to perform a hardware reset on the
* PHY to take it out of reset.
*/
if (ret_val)
goto out;
} else {
}
if (ret_val)
goto out;
/*
* Setup autoneg and flow control advertisement and perform
* autonegotiation.
*/
if (ret_val)
goto out;
} else {
/*
* PHY will be set to 10H, 10F, 100H or 100F
* depending on user settings.
*/
DEBUGOUT("Forcing Speed and Duplex\n");
if (ret_val) {
DEBUGOUT("Error Forcing Speed and Duplex\n");
goto out;
}
}
/*
* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
10,
&link);
if (ret_val)
goto out;
if (link) {
DEBUGOUT("Valid link established!!!\n");
/* Config the MAC and PHY after link is up */
} else {
if (ret_val)
goto out;
}
} else {
DEBUGOUT("Unable to establish link!!!\n");
}
out:
return (ret_val);
}
/*
* e1000_setup_fiber_link_82543 - Setup link for fiber
* @hw: pointer to the HW structure
*
* Configures collision distance and flow control for fiber links. Upon
* successful setup, poll for link.
*/
static s32
{
DEBUGFUNC("e1000_setup_fiber_link_82543");
/* Take the link out of reset */
ctrl &= ~E1000_CTRL_LRST;
if (ret_val)
goto out;
DEBUGOUT("Auto-negotiation enabled\n");
msec_delay(1);
/*
* For these adapters, the SW definable pin 1 is cleared when the
* optics detect a signal. If we have a signal, then poll for a
* "Link-Up" indication.
*/
} else {
DEBUGOUT("No signal detected\n");
}
out:
return (ret_val);
}
/*
* e1000_check_for_copper_link_82543 - Check for link (Copper)
* @hw: pointer to the HW structure
*
* Checks the phy for link, if link exists, do the following:
* - check for downshift
* - do polarity workaround (if necessary)
* - configure collision distance
* - configure flow control after link up
* - configure tbi compatibility
*/
static s32
{
bool link;
DEBUGFUNC("e1000_check_for_copper_link_82543");
if (!mac->get_link_status) {
goto out;
}
if (ret_val)
goto out;
if (!link)
goto out; /* No link detected */
mac->get_link_status = false;
(void) e1000_check_downshift_generic(hw);
/*
* we have already determined whether we have link or not.
*/
/*
* If speed and duplex are forced to 10H or 10F, then we will
* implement the polarity reversal workaround. We disable
* interrupts first, and upon returning, place the devices
* interrupt state to its previous value except for the link
* status change interrupt which will happened due to the
* execution of this workaround.
*/
}
goto out;
}
/*
* We have a M88E1000 PHY and Auto-Neg is enabled. If we
* have Si on board that is 82544 or newer, Auto
* configuration. So we only need to configure Collision
* Distance in the MAC. Otherwise, we need to force
* settings.
*/
else {
if (ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
goto out;
}
}
/*
* Configure Flow Control now that Auto-Neg has completed.
* First, we need to restore the desired flow control
* settings because we may have had to re-autoneg with a
* different link partner.
*/
if (ret_val) {
DEBUGOUT("Error configuring flow control\n");
}
/*
* At this point we know that we are on copper and we have
* auto-negotiated link. These are conditions for checking the link
* partner capability register. We use the link speed to determine if
* TBI compatibility needs to be turned on or off. If the link is not
* at gigabit speed, then TBI compatibility is not needed. If we are
* at gigabit speed, we turn on TBI compatibility.
*/
if (ret_val) {
DEBUGOUT("Error getting link speed and duplex\n");
return (ret_val);
}
if (speed != SPEED_1000) {
/*
* If link speed is not set to gigabit speed,
* we do not need to enable TBI compatibility.
*/
if (e1000_tbi_sbp_enabled_82543(hw)) {
/*
* If we previously were in the mode,
* turn it off.
*/
e1000_set_tbi_sbp_82543(hw, false);
rctl &= ~E1000_RCTL_SBP;
}
} else {
/*
* If TBI compatibility is was previously off,
* turn it on. For compatibility with a TBI link
* partner, we will store bad packets. Some
* frames have an additional byte on the end and
* will look like CRC errors to to the hardware.
*/
if (!e1000_tbi_sbp_enabled_82543(hw)) {
e1000_set_tbi_sbp_82543(hw, true);
rctl |= E1000_RCTL_SBP;
}
}
}
out:
return (ret_val);
}
/*
* e1000_check_for_fiber_link_82543 - Check for link (Fiber)
* @hw: pointer to the HW structure
*
* Checks for link up on the hardware. If link is not up and we have
* a signal, then we need to force link up.
*/
static s32
{
DEBUGFUNC("e1000_check_for_fiber_link_82543");
/*
* If we don't have link (auto-negotiation failed or link partner
* cannot auto-negotiate), the cable is plugged in (we have signal),
* and our link partner is not trying to auto-negotiate with us (we
* are receiving idles or data), we need to force link up. We also
* need to give auto-negotiation time to complete, in case the cable
* was just plugged in. The autoneg_failed flag does this.
*/
/* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
(!(status & E1000_STATUS_LU)) &&
(!(rxcw & E1000_RXCW_C))) {
if (mac->autoneg_failed == 0) {
ret_val = 0;
goto out;
}
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
/* Disable auto-negotiation in the TXCW register */
/* Force link-up and also force full-duplex. */
/* Configure Flow Control after forcing link up. */
if (ret_val) {
DEBUGOUT("Error configuring flow control\n");
goto out;
}
/*
* If we are forcing link and we are receiving /C/ ordered
* sets, re-enable auto-negotiation in the TXCW register
* and disable forced link in the Device Control register
* in an attempt to auto-negotiate with our link partner.
*/
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
mac->serdes_has_link = true;
}
out:
return (ret_val);
}
/*
* e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
* @hw: pointer to the HW structure
*
* For the 82543 silicon, we need to set the MAC to match the settings
* of the PHY, even if the PHY is auto-negotiating.
*/
static s32
{
DEBUGFUNC("e1000_config_mac_to_phy_82543");
goto out;
/* Set the bits to force speed and duplex */
/*
* Set up duplex in the Device Control and Transmit Control
* registers depending on negotiated values.
*/
if (ret_val)
goto out;
ctrl &= ~E1000_CTRL_FD;
if (phy_data & M88E1000_PSSR_DPLX)
ctrl |= E1000_CTRL_FD;
/*
* Set up speed in the Device Control register depending on
* negotiated values.
*/
out:
return (ret_val);
}
/*
* e1000_write_vfta_82543 - Write value to VLAN filter table
* @hw: pointer to the HW structure
* @offset: the 32-bit offset in which to write the value to.
* @value: the 32-bit value to write at location offset.
*
* This writes a 32-bit value to a 32-bit offset in the VLAN filter
* table.
*/
static void
{
DEBUGFUNC("e1000_write_vfta_82543");
} else {
}
}
/*
* e1000_mta_set_82543 - Set multicast filter table address
* @hw: pointer to the HW structure
* @hash_value: determines the MTA register and bit to set
*
* The multicast table address is a register array of 32-bit registers.
* The hash_value is used to determine what register the bit is in, the
* current value is read, the new bit is OR'd in and the new value is
* written back into the register.
*/
static void
{
DEBUGFUNC("e1000_mta_set_82543");
/*
* If we are on an 82544 and we are trying to write an odd offset
* in the MTA, save off the previous entry before writing and
* restore the old value after writing.
*/
} else {
}
}
/*
* e1000_led_on_82543 - Turn on SW controllable LED
* @hw: pointer to the HW structure
*
* Turns the SW defined LED on.
*/
static s32
{
DEBUGFUNC("e1000_led_on_82543");
/* Clear SW-definable Pin 0 to turn on the LED */
ctrl &= ~E1000_CTRL_SWDPIN0;
} else {
/* Fiber 82544 and all 82543 use this method */
}
return (E1000_SUCCESS);
}
/*
* e1000_led_off_82543 - Turn off SW controllable LED
* @hw: pointer to the HW structure
*
* Turns the SW defined LED off.
*/
static s32
{
DEBUGFUNC("e1000_led_off_82543");
/* Set SW-definable Pin 0 to turn off the LED */
} else {
ctrl &= ~E1000_CTRL_SWDPIN0;
}
return (E1000_SUCCESS);
}
/*
* e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
* @hw: pointer to the HW structure
*
* Clears the hardware counters by reading the counter registers.
*/
static void
{
DEBUGFUNC("e1000_clear_hw_cntrs_82543");
}