e1000_82540.c revision 57ef6f696a98dddd9434e80a654341edd5316bf1
/*
* This file is provided under a CDDLv1 license. When using or
* redistributing this file, you may do so under this license.
* In redistributing this file this license must be included
* and no other modification of this header file is permitted.
*
* CDDL LICENSE SUMMARY
*
* Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
*
* The contents of this file are subject to the terms of Version
* 1.0 of the Common Development and Distribution License (the "License").
*
* You should have received a copy of the License with this software.
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDLv1.
*/
/*
* IntelVersion: 1.57 v3-1-10-1_2009-9-18_Release14-6
*/
/*
* 82540EM Gigabit Ethernet Controller
* 82540EP Gigabit Ethernet Controller
* 82545EM Gigabit Ethernet Controller (Copper)
* 82545EM Gigabit Ethernet Controller (Fiber)
* 82545GM Gigabit Ethernet Controller
* 82546EB Gigabit Ethernet Controller (Copper)
* 82546EB Gigabit Ethernet Controller (Fiber)
* 82546GB Gigabit Ethernet Controller
*/
#include "e1000_api.h"
/*
* e1000_init_phy_params_82540 - Init PHY func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
/* Function Pointers */
if (ret_val)
goto out;
/* Verify phy id */
case e1000_82540:
case e1000_82545:
case e1000_82545_rev_3:
case e1000_82546:
case e1000_82546_rev_3:
break;
/* Fall Through */
default:
ret_val = -E1000_ERR_PHY;
goto out;
}
out:
return (ret_val);
}
/*
* e1000_init_nvm_params_82540 - Init NVM func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_nvm_params_82540");
break;
break;
default:
break;
}
/* Function Pointers */
return (E1000_SUCCESS);
}
/*
* e1000_init_mac_params_82540 - Init MAC func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_mac_params_82540");
/* Set media type */
break;
break;
default:
break;
}
/* Set mta register count */
/* Set rar entry count */
/* Function pointers */
/* function id */
/* reset */
/* hw initialization */
/* link setup */
/* physical interface setup */
/* check for link */
case e1000_media_type_copper:
break;
case e1000_media_type_fiber:
break;
break;
default:
goto out;
}
/* link info */
/* multicast address update */
/* writing VFTA */
/* clearing VFTA */
/* setting MTA */
/* ID LED init */
/* setup LED */
/* read mac address */
/* cleanup LED */
/* clear hardware counters */
out:
return (ret_val);
}
/*
* e1000_init_function_pointers_82540 - Init func ptrs.
* @hw: pointer to the HW structure
*
* Called to initialize all function pointers and parameters.
*/
void
{
DEBUGFUNC("e1000_init_function_pointers_82540");
}
/*
* e1000_reset_hw_82540 - Reset hardware
* @hw: pointer to the HW structure
*
* This resets the hardware into a known state.
*/
static s32
{
DEBUGFUNC("e1000_reset_hw_82540");
DEBUGOUT("Masking off all interrupts\n");
/*
* Delay to allow any outstanding PCI transactions to complete
* before resetting the device.
*/
msec_delay(10);
DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
case e1000_82545_rev_3:
case e1000_82546_rev_3:
break;
default:
/*
* These controllers can't ack the 64-bit write when
* issuing the reset, so we use IO-mapping as a
* workaround to issue the reset.
*/
break;
}
/* Wait for EEPROM reload */
msec_delay(5);
/* Disable HW ARPs on ASF enabled adapters */
manc &= ~E1000_MANC_ARP_EN;
return (ret_val);
}
/*
* e1000_init_hw_82540 - Initialize hardware
* @hw: pointer to the HW structure
*
* This inits the hardware readying it for operation.
*/
static s32
{
u16 i;
DEBUGFUNC("e1000_init_hw_82540");
/* Initialize identification LED */
if (ret_val) {
/* EMPTY */
DEBUGOUT("Error initializing identification LED\n");
/* This is not fatal and we should not stop init due to this */
}
/* Disabling VLAN filtering */
DEBUGOUT("Initializing the IEEE VLAN\n");
/* Setup the receive address. */
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++) {
/*
* Avoid back to back register writes by adding the register
* read (flush). This is to protect against some strange
* bridge configurations that may issue Memory Write Block
* (MWB) to our register space. The *_rev_3 hardware at
* least doesn't respond correctly to every other dword in an
* MWB to our register space.
*/
}
/* Setup link and flow control */
/*
* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
*/
/*
* Relaxed ordering must be disabled to avoid a parity
* error crash in a PCI slot.
*/
}
return (ret_val);
}
/*
* e1000_setup_copper_link_82540 - Configure copper link settings
* @hw: pointer to the HW structure
*
* Calls the appropriate function to configure the link for auto-neg or forced
* speed and duplex. Then we check for link, once link is established calls
* to configure collision distance and flow control are called. If link is
* not established, we return -E1000_ERR_PHY (-2).
*/
static s32
{
DEBUGFUNC("e1000_setup_copper_link_82540");
ctrl |= E1000_CTRL_SLU;
if (ret_val)
goto out;
ret_val =
if (ret_val)
goto out;
data |= 0x00000008;
ret_val =
if (ret_val)
goto out;
}
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* @hw: pointer to the HW structure
*
* Set the output amplitude to the value in the EEPROM and adjust the VCO
* speed to improve Bit Error Rate (BER) performance. Configures collision
* distance and flow control for fiber and serdes links. Upon successful
* setup, poll for link.
*/
static s32
{
DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
case e1000_82545_rev_3:
case e1000_82546_rev_3:
/*
* If we're on serdes media, adjust the output
* amplitude to value set in the EEPROM.
*/
if (ret_val)
goto out;
}
/* Adjust VCO speed to improve BER performance */
if (ret_val)
goto out;
default:
break;
}
out:
return (ret_val);
}
/*
* e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
* @hw: pointer to the HW structure
*
* Adjust the SERDES output amplitude based on the EEPROM settings.
*/
static s32
{
DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
if (ret_val)
goto out;
if (nvm_data != NVM_RESERVED_WORD) {
/* Adjust serdes output amplitude only. */
nvm_data);
if (ret_val)
goto out;
}
out:
return (ret_val);
}
/*
* e1000_set_vco_speed_82540 - Set VCO speed for better performance
* @hw: pointer to the HW structure
*
* Set the VCO speed to improve Bit Error Rate (BER) performance.
*/
static s32
{
u16 default_page = 0;
DEBUGFUNC("e1000_set_vco_speed_82540");
/* Set PHY register 30, page 5, bit 8 to 0 */
&default_page);
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
/* Set PHY register 30, page 4, bit 11 to 1 */
if (ret_val)
goto out;
if (ret_val)
goto out;
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* e1000_set_phy_mode_82540 - Set PHY to class A mode
* @hw: pointer to the HW structure
*
* Sets the PHY to class A mode and assumes the following operations will
* follow to enable the new class mode:
* 1. Do a PHY soft reset.
* 2. Restart auto-negotiation or force link.
*/
static s32
{
DEBUGFUNC("e1000_set_phy_mode_82540");
goto out;
if (ret_val) {
ret_val = -E1000_ERR_PHY;
goto out;
}
0x000B);
if (ret_val) {
ret_val = -E1000_ERR_PHY;
goto out;
}
0x8104);
if (ret_val) {
ret_val = -E1000_ERR_PHY;
goto out;
}
phy->reset_disable = false;
}
out:
return (ret_val);
}
/*
* e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
* @hw: pointer to the HW structure
*
* In the case of a PHY power down to save power, or to turn off link during a
* driver unload, or wake on lan is not enabled, remove the link.
*/
static void
{
/* If the management interface is not enabled, then power down */
}
/*
* e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
* @hw: pointer to the HW structure
*
* Clears the hardware counters by reading the counter registers.
*/
static void
{
DEBUGFUNC("e1000_clear_hw_cntrs_82540");
}
/*
* e1000_read_mac_addr_82540 - Read device MAC address
* @hw: pointer to the HW structure
*
* Reads the device MAC address from the EEPROM and stores the value.
* Since devices with two ports use the same EEPROM, we increment the
* last bit in the MAC address for the second port.
*
* This version is being used over generic because of customer issues
* with VmWare and Virtual Box when using generic. It seems in
* the emulated 82545, RAR[0] does NOT have a valid address after a
* reset, this older method works and using this breaks nothing for
* these legacy adapters.
*/
{
DEBUGFUNC("e1000_read_mac_addr");
for (i = 0; i < ETH_ADDR_LEN; i += 2) {
offset = i >> 1;
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
goto out;
}
}
/* Flip last bit of mac address if we're on second port */
for (i = 0; i < ETH_ADDR_LEN; i++)
out:
return (ret_val);
}