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/*$FreeBSD$*/
#ifndef _E1000_ICH8LAN_H_
#define _E1000_ICH8LAN_H_
/* Requires up to 10 seconds when MNG might be accessing part. */
#define ICH_CYCLE_READ 0
/* FW established a valid mode */
/* Shared Receive Address Registers */
(ID_LED_OFF1_OFF2 << 8) | \
(ID_LED_OFF1_ON2 << 4) | \
/* FEXT register bit definition */
/* bit for disabling packet buffer read */
/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
((reg) & MAX_PHY_REG_ADDRESS))
/* PHY Wakeup Registers and defines */
/* Half-duplex collision counts */
#define K1_ENTRY_LATENCY 0
/* SMBus Control Phy Register */
/* I218 Ultra Low Power Configuration 1 Register */
/* enable ULP even if when phy powered down via lanphypc */
/* disable clear of sticky ULP on PERST */
/* SMBus Address Phy Register */
/* Strapping Option Register - RO */
/* OEM Bits Phy Register */
/* KMRN Mode Control */
/* KMRN FIFO Control and Status */
/* PHY Power Management Control */
/* Inband Control */
/* Low Power Idle GPIO Control */
/* PHY Low Power Idle Control */
/* 82579 DFT Control */
/* Extended Management Interface (EMI) Registers */
/* Intel Rapid Start Technology Support */
/* Receive Address Initial CRC Calculation */
/* Latency Tolerance Reporting */
/* Proprietary Latency Tolerance Reporting PCI Capability */
/* OBFF Control & Threshold Defines */
bool state);
#endif /* _E1000_ICH8LAN_H_ */