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/*$FreeBSD$*/
#ifndef _E1000_DEFINES_H_
#define _E1000_DEFINES_H_
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
/* Definitions for power management and wakeup registers */
/* Wake Up Control */
/* Wake Up Filter Control */
/* Wake Up Status */
/* Extended Device Control */
/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
/* Physical Func Reset Done Indication */
/* Offset of the link mode field in Ctrl Ext register */
/* Receive Descriptor bit definitions */
/* mask to determine if packets should be dropped due to frame errors */
#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
E1000_RXD_ERR_CE | \
E1000_RXD_ERR_SE | \
/* Same mask, but for extended and packet split descriptors */
#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
/* Management Control */
/* Enable MAC address filtering */
/* Enable MNG packets to host memory */
/* Receive Control */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
/* Use byte values for the following shift parameters
* Usage:
* psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
* E1000_PSRCTL_BSIZE0_MASK) |
* ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
* E1000_PSRCTL_BSIZE1_MASK) |
* ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
* E1000_PSRCTL_BSIZE2_MASK) |
* ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
* E1000_PSRCTL_BSIZE3_MASK))
* where value0 = [128..16256], default=256
* value1 = [1024..64512], default=4096
* value2 = [0..64512], default=4096
* value3 = [0..64512], default=0
*/
/* SWFW_SYNC Definitions */
/* Device Control */
#define E1000_PCS_LCTL_FSV_10 0
/* Device Status */
/* Constants used to interpret the masked PCI-X bus speed. */
/* 1000/H is not supported, nor spec-compliant. */
#define E1000_ALL_SPEED_DUPLEX ( \
#define E1000_ALL_NOT_GIG ( \
/* LED Control */
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
/* Transmit Descriptor bit definitions */
/* Transmit Control */
/* Transmit Arbitration Count */
/* SerDes Control */
/* Receive Checksum Control */
/* Header split receive */
/* Collision related configuration parameters */
/* Default values for the transmit IPG register */
/* Ethertype field values */
/* Extended Configuration Control and Size */
/* Low Power IDLE Control */
/* PBA constants */
/* Uncorrectable/correctable ECC Error counts and enable bits */
/* SW Semaphore Register */
/* Interrupt Cause Read */
/* If this bit asserted, the driver should claim the interrupt */
/* PBA ECC Register */
/* Extended Interrupt Cause Read */
/* TCP Timer */
/* This defines the bits that are set in the Interrupt Mask
* o RXT0 = Receiver Timer Interrupt (ring 0)
* o TXDW = Transmit Descriptor Written Back
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
* o LSC = Link Status Change
*/
#define IMS_ENABLE_MASK ( \
E1000_IMS_RXT0 | \
E1000_IMS_TXDW | \
E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ | \
/* Interrupt Mask Set */
/* Extended Interrupt Mask Set */
/* Interrupt Cause Set */
/* Extended Interrupt Cause Set */
/* E1000_EITR_CNT_IGNR is only for 82576 and newer */
/* Transmit Descriptor Control */
/* Enable the counting of descriptors still to be processed. */
/* Flow Control Constants */
/* 802.1q VLAN Packet Size */
/* Receive Address
* Registers) holds the directed and multicast addresses that we monitor.
* Technically, we have 16 spots. However, we reserve one of these spots
* (RAR[15]) for our directed address used by controllers with
* manageability enabled, allowing us room for 15 multicast addresses.
*/
/* Error Codes */
#define E1000_SUCCESS 0
/* Loop limit on how long we wait for auto-negotiation to complete */
/* Number of 100 microseconds we wait for PCI Express master disable */
/* Number of milliseconds we wait for PHY configuration done after MAC reset */
/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
/* Number of milliseconds for NVM auto read done after MAC reset. */
/* Flow Control */
/* Transmit Configuration Word */
/* Receive Configuration Word */
/* HH Time Sync */
/* TUPLE Filtering Configuration */
/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
/* I350 EEE defines */
/* EEE status */
/* PCI Express Control */
/* mPHY address control and data registers */
/* AFE CSR Offset for PCS CLK */
/* Override for near end digital loopback. */
/* PHY Control Register */
/* PHY Status Register */
/* Autoneg Advertisement Register */
/* Link Partner Ability Register (Base Page) */
/* Autoneg Expansion Register */
/* 1000BASE-T Control Register */
/* 1=Configure PHY as Master 0=Configure PHY as Slave */
/* 1000BASE-T Status Register */
/* PHY Registers defined by IEEE */
/* NVM Control */
/* NVM Addressing bits based on type 0=small, 1=large */
/* Secure FLASH mode requires removing MSb */
/* Firmware code revision field word offset*/
/* NVM Word Offsets */
/* Mask bits for fields in Word 0x24 of the NVM */
/* Offset of Link Mode bits for 82575/82576 */
/* Offset of Link Mode bits for 82580 up */
/* Mask bits for fields in Word 0x0f of the NVM */
/* Mask bits for fields in Word 0x1a of the NVM */
/* Mask bits for fields in Word 0x03 of the EEPROM */
/* length of string needed to store PBA number */
/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
/* PBA (printed board assembly) number words */
/* NVM Commands - Microwire */
/* NVM Commands - SPI */
/* SPI NVM Status Register */
/* Word definitions for ID LED Settings */
(ID_LED_OFF1_OFF2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \
#ifndef ETH_ADDR_LEN
#endif
/* Bit definitions for valid PHY IDs.
* I = Integrated
* E = External
*/
/* M88E1000 Specific Registers */
/* M88E1000 PHY Specific Control Register */
/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
/* Auto crossover enabled all speeds */
/* M88E1000 PHY Specific Status Register */
/* 0 = <50M
* 1 = 50-80M
* 2 = 80-110M
* 3 = 110-140M
* 4 = >140M
*/
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master
*/
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the slave
*/
/* Intel I347AT4 Registers */
/* I347AT4 Extended PHY Specific Control Register */
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master
*/
/* I347AT4 PHY Cable Diagnostics Control */
/* M88E1112 only registers */
/* M88EC018 Rev 2 specific DownShift settings */
/* BME1000 PHY Specific Control Register */
/* Bits...
* 15-5: page
* 4-0: register offset
*/
/* GG82563 Specific Registers */
/* MAC Specific Control Register */
/* Page 193 - Port Control Registers */
/* Kumeran Mode Control */
/* Page 194 - KMRN Registers */
/* MDI Control */
/* SerDes Control */
/* LinkSec register fields */
/* Tx Rate-Scheduler Config fields */
#define E1000_RTTBCNRC_RF_INT_MASK \
/* DMA Coalescing register fields */
/* DMA Coalescing Watchdog Timer */
/* DMA Coalescing Rx Threshold */
/* Lx when no PCIe transactions */
/* DMA Coalescing BMC-to-OS Watchdog Enable */
/* DMA Coalescing Transmit Threshold */
/* Rx Traffic Rate Threshold */
/* Rx packet rate in current window */
/* DMA Coal Rx Traffic Current Count */
/* Flow ctrl Rx Threshold High val */
/* Lx power decision based on DMA coal */
/* Proxy Filter Control */
/* Proxy Status */
/* Firmware Status */
/* VF Control */
/* Lan ID bit field offset in status register */
#define E1000_UNUSEDARG
#ifndef ERROR_REPORT
#endif /* ERROR_REPORT */
/*
* illumos additions
*/
#endif /* _E1000_DEFINES_H_ */