/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_DMFE_H
#define _SYS_DMFE_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/* Chip ID */
/* The 9102 and 9102A are distinguished by revision ID */
/* Streams */
/* address within setup buffer */
/*
*
* These structures are not actually used; they are just here to show
* the layout of the descriptor entries used by the DMFE chip hardware
* (we do use "sizeof" these structures). The code uses the #defined
* offsets below to access the various members of the descriptors, via
* the DDI access functions (remember the DMFE h/w is little-endian).
*/
struct rx_desc_type {
};
struct tx_desc_type {
};
/*
*/
#define DESC0 0
/*
* Receive descriptor description
*/
/* desc0 bit definitions */
/* desc1 bit definitions */
/*
* Transmit descriptor description
*/
/* desc0 bit definitions */
/* desc1 bit definitions */
/* Device-defined PCI config space registers */
/* Operating registers in I/O or MEMORY space */
/* Bit descriptions of CSR registers */
/* BUS_MODE_REG, CSR0 */
/* Multiple PCI cycles */
/* STATUS_REG, CSR5 */
/* OPN_REG , CSR6 */
/* INT_MASK_REG , CSR7 */
/*
* Use the values defined for the INT_STATUS_MASK bits (0..16)
* of CSR5. The remaining bits (17..31) are not used.
*/
/* MISSED_FRAME_REG, CSR8 */
/* GPR Timer reg, CSR11 */
/* PHY Status reg, CSR12 */
/* Sample Frame Access reg, CSR13 */
/* Sample Frame Data reg, CSR14, when CSR13 is set to DIAG_RESET */
/* CSR15 */
/* SROM access definitions */
/* MII access definitions */
/* DMFE IOCTLS */
/* argument structure for above */
typedef struct {
int loopback;
} loopback_t;
#define DMFE_LOOPBACK_OFF 0
#ifdef __cplusplus
}
#endif
#endif /* _SYS_DMFE_H */