/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
*/
/*
* Chelsio Terminator 4 (T4) Firmware interface header file.
*
* Copyright (C) 2009-2013 Chelsio Communications. All rights reserved.
*
* Written by felix marti (felix@chelsio.com)
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
* release for licensing terms and conditions.
*/
#ifndef _T4FW_INTERFACE_H_
#define _T4FW_INTERFACE_H_
/*
* ******************************
* R E T U R N V A L U E S
* ******************************
*/
enum fw_retval {
};
/*
* ******************************
* W O R K R E Q U E S T s
* ******************************
*/
enum fw_wr_opcodes {
};
/*
* Generic work request header flit0
*/
struct fw_wr_hdr {
};
/* work request opcode (hi) */
/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
#define G_FW_WR_ATOMIC(x) \
(((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
/*
* flush flag (hi) - firmware flushes flushable work request buffered
* in the flow context.
*/
#define G_FW_WR_FLUSH(x) \
(((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
/* completion flag (hi) - firmware generates a cpl_fw6_ack */
#define G_FW_WR_COMPL(x) \
(((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
/* work request immediate data lengh (hi) */
#define S_FW_WR_IMMDLEN 0
#define G_FW_WR_IMMDLEN(x) \
(((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
/* egress queue status update to associated ingress queue entry (lo) */
/* egress queue status update to egress queue status entry (lo) */
/* flow context identifier (lo) */
/* length in units of 16-bytes (lo) */
#define S_FW_WR_LEN16 0
/*
* valid filter configurations for compressed tuple
* Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
* FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
* E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
*/
/* filter wr reply code in cookie in CPL_SET_TCB_RPL */
enum fw_filter_wr_cookie {
};
struct fw_filter_wr {
};
#define G_FW_FILTER_WR_TID(x) \
(((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
#define G_FW_FILTER_WR_RQTYPE(x) \
(((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
#define G_FW_FILTER_WR_NOREPLY(x) \
(((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
#define S_FW_FILTER_WR_IQ 0
#define G_FW_FILTER_WR_IQ(x) \
(((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
#define G_FW_FILTER_WR_DEL_FILTER(x) \
(((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
#define G_FW_FILTER_WR_RPTTID(x) \
(((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
#define G_FW_FILTER_WR_DROP(x) \
(((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
#define G_FW_FILTER_WR_DIRSTEER(x) \
(((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
#define G_FW_FILTER_WR_MASKHASH(x) \
(((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
#define G_FW_FILTER_WR_DIRSTEERHASH(x) \
(((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
#define G_FW_FILTER_WR_LPBK(x) \
(((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
#define G_FW_FILTER_WR_DMAC(x) \
(((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
#define G_FW_FILTER_WR_SMAC(x) \
(((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
#define G_FW_FILTER_WR_INSVLAN(x) \
(((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
#define G_FW_FILTER_WR_RMVLAN(x) \
(((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
#define G_FW_FILTER_WR_HITCNTS(x) \
(((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
#define G_FW_FILTER_WR_TXCHAN(x) \
(((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
#define G_FW_FILTER_WR_PRIO(x) \
(((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
#define S_FW_FILTER_WR_L2TIX 0
#define G_FW_FILTER_WR_L2TIX(x) \
(((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
#define G_FW_FILTER_WR_FRAG(x) \
(((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
#define G_FW_FILTER_WR_FRAGM(x) \
(((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
#define G_FW_FILTER_WR_IVLAN_VLD(x) \
(((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
#define G_FW_FILTER_WR_OVLAN_VLD(x) \
(((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
#define G_FW_FILTER_WR_IVLAN_VLDM(x) \
(((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
#define G_FW_FILTER_WR_OVLAN_VLDM(x) \
(((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
#define G_FW_FILTER_WR_RX_CHAN(x) \
(((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
#define S_FW_FILTER_WR_RX_RPL_IQ 0
#define G_FW_FILTER_WR_RX_RPL_IQ(x) \
(((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
#define G_FW_FILTER_WR_MACI(x) \
(((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
#define G_FW_FILTER_WR_MACIM(x) \
(((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
#define G_FW_FILTER_WR_FCOE(x) \
(((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
#define G_FW_FILTER_WR_FCOEM(x) \
(((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
#define G_FW_FILTER_WR_PORT(x) \
(((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
#define G_FW_FILTER_WR_PORTM(x) \
(((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
#define G_FW_FILTER_WR_MATCHTYPE(x) \
(((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
#define S_FW_FILTER_WR_MATCHTYPEM 0
#define G_FW_FILTER_WR_MATCHTYPEM(x) \
(((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
struct fw_ulptx_wr {
};
struct fw_tp_wr {
};
struct fw_eth_tx_pkt_wr {
};
#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
(((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
struct fw_eth_tx_pkts_wr {
};
struct fw_eth_tx_uo_wr {
};
struct fw_eq_flush_wr {
};
struct fw_ofld_connection_wr {
struct fw_ofld_connection_le {
union fw_ofld_connection_leip {
struct fw_ofld_connection_le_ipv4 {
} ipv4;
struct fw_ofld_connection_le_ipv6 {
} ipv6;
} u;
} le;
struct fw_ofld_connection_tcb {
} tcb;
};
#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
#define G_FW_OFLD_CONNECTION_WR_CPL(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
#define S_FW_OFLD_CONNECTION_WR_ASTID 0
#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
(((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
enum fw_flowc_mnem_tcpstate {
/* haven't gotten ACK for FIN and will resend FIN - equiv ESTAB */
/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
/* sent FIN and got FIN + ACK, waiting for FIN */
};
enum fw_flowc_mnem_uostate {
/* graceful close, after sending outstanding payload */
/* immediate close, after discarding outstanding payload */
};
enum fw_flowc_mnem {
};
struct fw_flowc_mnemval {
};
struct fw_flowc_wr {
#ifndef C99_NOT_SUPPORTED
#endif
};
#define S_FW_FLOWC_WR_NPARAMS 0
#define G_FW_FLOWC_WR_NPARAMS(x) \
(((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
struct fw_ofld_tx_data_wr {
};
#define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL)
#define G_FW_OFLD_TX_DATA_WR_SAVE(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE)
#define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH)
#define G_FW_OFLD_TX_DATA_WR_URGENT(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT)
#define G_FW_OFLD_TX_DATA_WR_MORE(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE)
#define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE)
#define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE)
#define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \
((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
#define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \
#define G_FW_OFLD_TX_DATA_WR_PROXY(x) \
(((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY)
struct fw_cmd_wr {
};
struct fw_eth_tx_pkt_vm_wr {
};
/*
* ************************************
* R I W O R K R E Q U E S T s
* ************************************
*/
enum fw_ri_wr_opcode {
};
enum fw_ri_wr_flags {
};
enum fw_ri_mpa_attrs {
};
enum fw_ri_qp_caps {
};
enum fw_ri_addr_type {
};
enum fw_ri_mem_perms {
};
enum fw_ri_stag_type {
};
enum fw_ri_data_op {
};
enum fw_ri_sgl_depth {
};
enum fw_ri_cqe_err {
/* attempt to invalidate a SMR */
/* attempt to invalidate a MR w MW */
/* ECC error detected when reading the PSTAG for a MW Invalidate */
/* pbl address out of bound : software error */
/* MO not zero for TERMINATE or READ_REQ */
/* RQE address out of bound : software error */
/* internel error (opcode mismatch) */
};
struct fw_ri_dsge_pair {
};
struct fw_ri_dsgl {
#ifndef C99_NOT_SUPPORTED
#endif
};
struct fw_ri_sge {
};
struct fw_ri_isgl {
#ifndef C99_NOT_SUPPORTED
#endif
};
struct fw_ri_immd {
#ifndef C99_NOT_SUPPORTED
#endif
};
struct fw_ri_tpte {
};
#define G_FW_RI_TPTE_VALID(x) \
(((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
#define G_FW_RI_TPTE_STAGKEY(x) \
(((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
#define G_FW_RI_TPTE_STAGSTATE(x) \
(((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
#define G_FW_RI_TPTE_STAGTYPE(x) \
(((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
#define S_FW_RI_TPTE_PDID 0
#define G_FW_RI_TPTE_PDID(x) \
(((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
#define G_FW_RI_TPTE_PERM(x) \
(((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
#define G_FW_RI_TPTE_REMINVDIS(x) \
(((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
#define G_FW_RI_TPTE_ADDRTYPE(x) \
(((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
#define G_FW_RI_TPTE_MWBINDEN(x) \
(((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
#define G_FW_RI_TPTE_PS(x) \
(((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
#define S_FW_RI_TPTE_QPID 0
#define G_FW_RI_TPTE_QPID(x) \
(((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
#define G_FW_RI_TPTE_NOSNOOP(x) \
(((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
#define S_FW_RI_TPTE_PBLADDR 0
#define G_FW_RI_TPTE_PBLADDR(x) \
(((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
#define G_FW_RI_TPTE_DCA(x) \
(((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
#define S_FW_RI_TPTE_MWBCNT_PSTAG 0
#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \
((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \
(((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
enum fw_ri_cqe_rxtx {
};
struct fw_ri_cqe {
union fw_ri_rxtx {
struct fw_ri_scqe {
} scqe;
struct fw_ri_rcqe {
} rcqe;
} u;
};
#define G_FW_RI_CQE_QPID(x) \
(((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID)
#define G_FW_RI_CQE_NOTIFY(x) \
(((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY)
#define G_FW_RI_CQE_STATUS(x) \
(((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS)
#define G_FW_RI_CQE_RXTX(x) \
(((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX)
#define S_FW_RI_CQE_TYPE 0
#define G_FW_RI_CQE_TYPE(x) \
(((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE)
enum fw_ri_res_type {
};
enum fw_ri_res_op {
};
struct fw_ri_res {
union fw_ri_restype {
struct fw_ri_res_sqrq {
} sqrq;
struct fw_ri_res_cq {
} cq;
} u;
};
struct fw_ri_res_wr {
#ifndef C99_NOT_SUPPORTED
#endif
};
#define S_FW_RI_RES_WR_NRES 0
#define G_FW_RI_RES_WR_NRES(x) \
(((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
#define G_FW_RI_RES_WR_FETCHSZM(x) \
(((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
#define G_FW_RI_RES_WR_STATUSPGNS(x) \
(((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
#define G_FW_RI_RES_WR_STATUSPGRO(x) \
(((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
#define G_FW_RI_RES_WR_FETCHNS(x) \
(((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
#define G_FW_RI_RES_WR_FETCHRO(x) \
(((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
#define G_FW_RI_RES_WR_HOSTFCMODE(x) \
(((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
#define G_FW_RI_RES_WR_CPRIO(x) \
(((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
#define G_FW_RI_RES_WR_ONCHIP(x) \
(((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
#define G_FW_RI_RES_WR_PCIECHN(x) \
(((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
#define S_FW_RI_RES_WR_IQID 0
#define G_FW_RI_RES_WR_IQID(x) \
(((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
#define G_FW_RI_RES_WR_DCAEN(x) \
(((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
#define G_FW_RI_RES_WR_DCACPU(x) \
(((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
#define G_FW_RI_RES_WR_FBMIN(x) \
(((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
#define G_FW_RI_RES_WR_FBMAX(x) \
(((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \
(((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \
(((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
#define S_FW_RI_RES_WR_EQSIZE 0
#define G_FW_RI_RES_WR_EQSIZE(x) \
(((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
#define G_FW_RI_RES_WR_IQANDST(x) \
(((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
#define G_FW_RI_RES_WR_IQANUS(x) \
(((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
#define G_FW_RI_RES_WR_IQANUD(x) \
(((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
#define S_FW_RI_RES_WR_IQANDSTINDEX 0
#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \
(((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
#define G_FW_RI_RES_WR_IQDROPRSS(x) \
(((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
#define G_FW_RI_RES_WR_IQGTSMODE(x) \
(((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
#define G_FW_RI_RES_WR_IQPCIECH(x) \
(((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
#define G_FW_RI_RES_WR_IQDCAEN(x) \
(((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
#define G_FW_RI_RES_WR_IQDCACPU(x) \
(((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
#define G_FW_RI_RES_WR_IQO(x) \
(((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
#define G_FW_RI_RES_WR_IQCPRIO(x) \
(((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
#define S_FW_RI_RES_WR_IQESIZE 0
#define G_FW_RI_RES_WR_IQESIZE(x) \
(((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
#define G_FW_RI_RES_WR_IQNS(x) \
(((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
#define G_FW_RI_RES_WR_IQRO(x) \
(((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
struct fw_ri_rdma_write_wr {
};
struct fw_ri_send_wr {
};
#define S_FW_RI_SEND_WR_SENDOP 0
#define G_FW_RI_SEND_WR_SENDOP(x) \
(((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
struct fw_ri_rdma_read_wr {
};
struct fw_ri_recv_wr {
};
struct fw_ri_bind_mw_wr {
};
#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \
(((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
#define G_FW_RI_BIND_MW_WR_NS(x) \
(((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
#define S_FW_RI_BIND_MW_WR_DCACPU 0
#define G_FW_RI_BIND_MW_WR_DCACPU(x) \
(((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
struct fw_ri_fr_nsmr_wr {
};
#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \
(((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
#define G_FW_RI_FR_NSMR_WR_NS(x) \
(((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
#define S_FW_RI_FR_NSMR_WR_DCACPU 0
#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
(((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
struct fw_ri_inv_lstag_wr {
};
struct fw_ri_send_immediate_wr {
};
#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0
#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
(((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
enum fw_ri_atomic_op {
};
struct fw_ri_atomic_wr {
};
#define S_FW_RI_ATOMIC_WR_ATOMICOP 0
#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \
(((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
#define S_FW_RI_ATOMIC_WR_AOPCODE 0
#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \
(((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
enum fw_ri_type {
};
enum fw_ri_init_p2ptype {
};
struct fw_ri_wr {
union fw_ri {
struct fw_ri_init {
union fw_ri_init_p2p {
} u;
} init;
struct fw_ri_fini {
} fini;
struct fw_ri_terminate {
} terminate;
} u;
};
#define G_FW_RI_WR_MPAREQBIT(x) \
(((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
#define G_FW_RI_WR_0BRRBIT(x) \
(((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
#define S_FW_RI_WR_P2PTYPE 0
#define G_FW_RI_WR_P2PTYPE(x) \
(((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
/*
* *******************************************
* F O i S C S I W O R K R E Q U E S T s
* *******************************************
*/
enum fw_chnet_ifconf_wr_subop {
};
struct fw_chnet_ifconf_wr {
struct fw_chnet_ifconf_params {
union fw_chnet_ifconf_addr_type {
struct fw_chnet_ifconf_ipv4 {
} ipv4;
struct fw_chnet_ifconf_ipv6 {
} ipv6;
} in_attr;
} param;
};
enum fw_foiscsi_session_type {
};
enum fw_foiscsi_auth_policy {
};
enum fw_foiscsi_auth_method {
};
enum fw_foiscsi_digest_type {
};
enum fw_foiscsi_wr_subop {
};
enum fw_foiscsi_ctrl_state {
};
struct fw_rdev_wr {
union rdev_entry {
struct fcoe_rdev_entry {
} fcoe_rdev;
struct iscsi_rdev_entry {
} iscsi_rdev;
} u;
};
#define S_FW_RDEV_WR_IMMDLEN 0
#define G_FW_RDEV_WR_IMMDLEN(x) \
(((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
#define G_FW_RDEV_WR_ALLOC(x) \
(((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
#define G_FW_RDEV_WR_FREE(x) \
(((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
#define G_FW_RDEV_WR_MODIFY(x) \
(((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
#define G_FW_RDEV_WR_FLOWID(x) \
(((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
#define S_FW_RDEV_WR_LEN16 0
#define G_FW_RDEV_WR_LEN16(x) \
(((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
#define G_FW_RDEV_WR_FLAGS(x) \
(((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
#define G_FW_RDEV_WR_GET_NEXT(x) \
(((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
#define S_FW_RDEV_WR_ASSOC_FLOWID 0
#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \
(((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
#define S_FW_RDEV_WR_REASON 0
#define G_FW_RDEV_WR_REASON(x) \
(((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
#define G_FW_RDEV_WR_RD_XFER_RDY(x) \
(((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
#define G_FW_RDEV_WR_WR_XFER_RDY(x) \
(((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
#define G_FW_RDEV_WR_FC_SP(x) \
(((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
#define S_FW_RDEV_WR_RPORT_TYPE 0
#define G_FW_RDEV_WR_RPORT_TYPE(x) \
(((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
#define G_FW_RDEV_WR_NPIV(x) \
(((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
#define G_FW_RDEV_WR_CLASS(x) \
(((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
#define G_FW_RDEV_WR_SEQ_DEL(x) \
(((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
#define G_FW_RDEV_WR_PRIO_PREEMP(x) \
(((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
#define G_FW_RDEV_WR_PREF(x) \
(((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
#define S_FW_RDEV_WR_QOS 0
#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \
(((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \
(((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
#define G_FW_RDEV_WR_IMAGE_PAIR(x) \
(((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
#define S_FW_RDEV_WR_ACC_RSP_CODE 0
#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \
(((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
#define G_FW_RDEV_WR_ENH_DISC(x) \
(((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \
(((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
#define G_FW_RDEV_WR_RETRY(x) \
(((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
#define G_FW_RDEV_WR_CONF_CMPL(x) \
(((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
#define G_FW_RDEV_WR_DATA_OVLY(x) \
(((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
#define S_FW_RDEV_WR_TGT 0
struct fw_foiscsi_node_wr {
};
#define S_FW_FOISCSI_NODE_WR_IMMDLEN 0
#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \
(((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
struct fw_foiscsi_ctrl_wr {
struct fw_foiscsi_sess_attr {
} sess_attr;
struct fw_foiscsi_conn_attr {
union fw_foiscsi_conn_attr_addr {
struct fw_foiscsi_conn_attr_ipv6 {
} ipv6_addr;
struct fw_foiscsi_conn_attr_ipv4 {
} ipv4_addr;
} u;
} conn_attr;
};
#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & \
#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \
#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \
#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \
#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \
#define G_FW_FOISCSI_CTRL_WR_ERL(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
struct fw_foiscsi_chap_wr {
};
/*
* *****************************************
* F O F C O E W O R K R E Q U E S T s
* *****************************************
*/
struct fw_fcoe_els_ct_wr {
};
#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
#define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0
#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
#define S_FW_FCOE_ELS_CT_WR_LEN16 0
#define G_FW_FCOE_ELS_CT_WR_LEN16(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
#define G_FW_FCOE_ELS_CT_WR_FL(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
#define S_FW_FCOE_ELS_CT_WR_SP 0
#define G_FW_FCOE_ELS_CT_WR_SP(x) \
(((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
/*
* ****************************************
* S C S I W O R K R E Q U E S T s
* (FOiSCSI and FCOE unified data path)
* ****************************************
*/
struct fw_scsi_write_wr {
union fw_scsi_write_priv {
struct fcoe_write_priv {
} fcoe;
struct iscsi_write_priv {
} iscsi;
} u;
};
#define G_FW_SCSI_WRITE_WR_OPCODE(x) \
(((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
#define S_FW_SCSI_WRITE_WR_IMMDLEN 0
#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \
(((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
#define G_FW_SCSI_WRITE_WR_FLOWID(x) \
(((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
#define S_FW_SCSI_WRITE_WR_LEN16 0
#define G_FW_SCSI_WRITE_WR_LEN16(x) \
(((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
#define G_FW_SCSI_WRITE_WR_CP_EN(x) \
(((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
#define G_FW_SCSI_WRITE_WR_CLASS(x) \
(((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
struct fw_scsi_read_wr {
union fw_scsi_read_priv {
struct fcoe_read_priv {
} fcoe;
struct iscsi_read_priv {
} iscsi;
} u;
};
#define G_FW_SCSI_READ_WR_OPCODE(x) \
(((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
#define S_FW_SCSI_READ_WR_IMMDLEN 0
#define G_FW_SCSI_READ_WR_IMMDLEN(x) \
(((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
#define G_FW_SCSI_READ_WR_FLOWID(x) \
(((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
#define S_FW_SCSI_READ_WR_LEN16 0
#define G_FW_SCSI_READ_WR_LEN16(x) \
(((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
#define G_FW_SCSI_READ_WR_CP_EN(x) \
(((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
#define G_FW_SCSI_READ_WR_CLASS(x) \
(((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
struct fw_scsi_cmd_wr {
union fw_scsi_cmd_priv {
struct fcoe_cmd_priv {
} fcoe;
struct iscsi_cmd_priv {
} iscsi;
} u;
};
#define G_FW_SCSI_CMD_WR_OPCODE(x) \
(((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
#define S_FW_SCSI_CMD_WR_IMMDLEN 0
#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \
(((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
#define G_FW_SCSI_CMD_WR_FLOWID(x) \
(((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
#define S_FW_SCSI_CMD_WR_LEN16 0
#define G_FW_SCSI_CMD_WR_LEN16(x) \
(((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
#define G_FW_SCSI_CMD_WR_CP_EN(x) \
(((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
#define G_FW_SCSI_CMD_WR_CLASS(x) \
(((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
struct fw_scsi_abrt_cls_wr {
};
#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \
(((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0
#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \
(((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
#define S_FW_SCSI_ABRT_CLS_WR_LEN16 0
#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \
(((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
(((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \
(((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0
#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
(((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \
struct fw_scsi_tgt_acc_wr {
union fw_scsi_tgt_acc_priv {
struct fcoe_tgt_acc_priv {
} fcoe;
struct iscsi_tgt_acc_priv {
} iscsi;
} u;
};
#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \
(((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0
#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \
(((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \
(((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
#define S_FW_SCSI_TGT_ACC_WR_LEN16 0
#define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \
(((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \
(((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \
(((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
struct fw_scsi_tgt_xmit_wr {
union fw_scsi_tgt_xmit_priv {
struct fcoe_tgt_xmit_priv {
} fcoe;
struct iscsi_tgt_xmit_priv {
} iscsi;
} u;
};
#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \
(((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0
#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \
(((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
#define S_FW_SCSI_TGT_XMIT_WR_LEN16 0
#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \
(((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \
(((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \
(((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
struct fw_scsi_tgt_rsp_wr {
union fw_scsi_tgt_rsp_priv {
struct fcoe_tgt_rsp_priv {
} fcoe;
struct iscsi_tgt_rsp_priv {
} iscsi;
} u;
};
#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \
(((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0
#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \
(((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \
(((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
#define S_FW_SCSI_TGT_RSP_WR_LEN16 0
#define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \
(((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \
(((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \
(((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
/*
* *******************
* C O M M A N D s
* *******************
*/
/*
* The maximum length of time, in miliseconds, that we expect any firmware
* command to take to execute and return a reply to the host. The RESET
* and INITIALIZE commands can take a fair amount of time to execute but
* most execute in far less time than this maximum. This constant is used
* by host software to determine how long to wait for a firmware command
* reply before declaring the firmware as dead/unreachable ...
*/
/*
* If a host driver does a HELLO and discovers that there's already a MASTER
* selected, we may have to wait for that MASTER to finish issuing RESET,
* configuration and INITIALIZE commands. Also, there's a possibility that
* our own HELLO may get lost if it happens right as the MASTER is issuign a
* RESET command, so we need to be willing to make a few retries of our HELLO.
*/
enum fw_cmd_opcodes {
};
enum fw_cmd_cap {
};
/*
* Generic command header flit0
*/
struct fw_cmd_hdr {
};
#define S_FW_CMD_LEN16 0
/*
* address spaces
*/
enum fw_ldst_addrspc {
};
/*
* MDIO VSC8634 register access control field
*/
enum fw_ldst_mdio_vsc8634_aid {
};
enum fw_ldst_mps_fid {
};
enum fw_ldst_func_access_ctl {
};
enum fw_ldst_func_mod_index {
};
struct fw_ldst_cmd {
union fw_ldst {
struct fw_ldst_addrval {
} addrval;
struct fw_ldst_idctxt {
} idctxt;
struct fw_ldst_mdio {
} mdio;
struct fw_ldst_mps {
} mps;
struct fw_ldst_func {
} func;
struct fw_ldst_pcie {
__u8 r;
} pcie;
struct fw_ldst_i2c {
} i2c;
struct fw_ldst_le {
} le;
} u;
};
#define S_FW_LDST_CMD_ADDRSPACE 0
#define G_FW_LDST_CMD_ADDRSPACE(x) \
(((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
#define G_FW_LDST_CMD_CYCLES(x) \
(((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
#define G_FW_LDST_CMD_MSG(x) \
(((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
#define G_FW_LDST_CMD_CTXTFLUSH(x) \
(((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
#define G_FW_LDST_CMD_PADDR(x) \
(((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
#define S_FW_LDST_CMD_MMD 0
#define G_FW_LDST_CMD_MMD(x) \
(((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
#define G_FW_LDST_CMD_FID(x) \
(((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
#define S_FW_LDST_CMD_CTL 0
#define G_FW_LDST_CMD_CTL(x) \
(((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL)
#define S_FW_LDST_CMD_RPLCPF 0
#define G_FW_LDST_CMD_RPLCPF(x) \
(((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
#define G_FW_LDST_CMD_CTRL(x) \
(((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
#define S_FW_LDST_CMD_FN 0
#define G_FW_LDST_CMD_SELECT(x) \
(((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
#define S_FW_LDST_CMD_NACCESS 0
#define G_FW_LDST_CMD_NACCESS(x) \
(((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
#define G_FW_LDST_CMD_NSET(x) \
(((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
#define G_FW_LDST_CMD_PID(x) \
(((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
struct fw_reset_cmd {
};
#define G_FW_RESET_CMD_HALT(x) \
(((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
enum {
};
struct fw_hello_cmd {
};
#define G_FW_HELLO_CMD_ERR(x) \
(((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
#define G_FW_HELLO_CMD_INIT(x) \
(((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
#define G_FW_HELLO_CMD_MASTERDIS(x) \
(((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
#define G_FW_HELLO_CMD_MASTERFORCE(x) \
(((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
#define G_FW_HELLO_CMD_MBMASTER(x) \
(((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \
(((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
#define G_FW_HELLO_CMD_MBASYNCNOT(x) \
(((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
#define G_FW_HELLO_CMD_STAGE(x) \
(((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
#define G_FW_HELLO_CMD_CLEARINIT(x) \
(((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
struct fw_bye_cmd {
};
struct fw_initialize_cmd {
};
enum fw_caps_config_hm {
};
/*
* The VF Register Map.
*
* The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
* bus module (PL) and CPU Interface Module (CIM) components are mapped via
* the Slice to Module Map Table (see below) in the Physical Function Register
* Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
* and Offset registers in the PF Register Map. The MBDATA base address is
* quite constrained as it determines the Mailbox Data addresses for both PFs
* and VFs, and therefore must fit in both the VF and PF Register Maps without
* overlapping other registers.
*/
enum fw_caps_config_nbm {
};
enum fw_caps_config_link {
};
enum fw_caps_config_switch {
};
enum fw_caps_config_nic {
};
enum fw_caps_config_toe {
};
enum fw_caps_config_rdma {
};
enum fw_caps_config_iscsi {
};
enum fw_caps_config_fcoe {
};
enum fw_memtype_cf {
};
struct fw_caps_config_cmd {
};
#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
(((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
(((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
(((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
/*
* params command mnemonics
*/
enum fw_params_mnem {
};
/*
* device parameters
*/
enum fw_params_param_dev {
/* reads the number of TIDs allocated by the device's Lookup Engine */
};
/*
* physical and virtual function parameters
*/
enum fw_params_param_pfvf {
};
/*
* dma queue parameters
*/
enum fw_params_param_dmaq {
};
/*
* dev bypass parameters; actions and modes
*/
enum fw_params_param_dev_bypass {
/* actions */
/* modes */
};
#define G_FW_PARAMS_MNEM(x) \
(((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
#define G_FW_PARAMS_PARAM_X(x) \
(((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
#define G_FW_PARAMS_PARAM_Y(x) \
(((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
#define S_FW_PARAMS_PARAM_Z 0
#define G_FW_PARAMS_PARAM_Z(x) \
(((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
#define S_FW_PARAMS_PARAM_XYZ 0
#define G_FW_PARAMS_PARAM_XYZ(x) \
(((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
#define S_FW_PARAMS_PARAM_YZ 0
#define G_FW_PARAMS_PARAM_YZ(x) \
(((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
struct fw_params_cmd {
struct fw_params_param {
};
#define G_FW_PARAMS_CMD_PFN(x) \
(((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
#define S_FW_PARAMS_CMD_VFN 0
#define G_FW_PARAMS_CMD_VFN(x) \
(((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
struct fw_pfvf_cmd {
};
#define G_FW_PFVF_CMD_PFN(x) \
(((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
#define S_FW_PFVF_CMD_VFN 0
#define G_FW_PFVF_CMD_VFN(x) \
(((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
#define G_FW_PFVF_CMD_NIQFLINT(x) \
(((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
#define S_FW_PFVF_CMD_NIQ 0
#define G_FW_PFVF_CMD_NIQ(x) \
(((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
#define G_FW_PFVF_CMD_TYPE(x) \
(((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
#define G_FW_PFVF_CMD_CMASK(x) \
(((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
#define G_FW_PFVF_CMD_PMASK(x) \
(((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
#define S_FW_PFVF_CMD_NEQ 0
#define G_FW_PFVF_CMD_NEQ(x) \
(((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
#define G_FW_PFVF_CMD_NVI(x) \
(((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
#define S_FW_PFVF_CMD_NEXACTF 0
#define G_FW_PFVF_CMD_NEXACTF(x) \
(((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
#define G_FW_PFVF_CMD_R_CAPS(x) \
(((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
#define G_FW_PFVF_CMD_WX_CAPS(x) \
(((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
#define S_FW_PFVF_CMD_NETHCTRL 0
#define G_FW_PFVF_CMD_NETHCTRL(x) \
(((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
/*
* ingress queue type; the first 1K ingress queues can have associated 0,
* 1 or 2 free lists and an interrupt, all other ingress queues lack these
* capabilities
*/
enum fw_iq_type {
};
struct fw_iq_cmd {
};
#define S_FW_IQ_CMD_VFN 0
#define G_FW_IQ_CMD_ALLOC(x) \
(((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
#define G_FW_IQ_CMD_MODIFY(x) \
(((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
#define G_FW_IQ_CMD_IQSTART(x) \
(((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
#define G_FW_IQ_CMD_IQSTOP(x) \
(((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
#define G_FW_IQ_CMD_IQASYNCH(x) \
(((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
#define G_FW_IQ_CMD_IQANDST(x) \
(((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
#define G_FW_IQ_CMD_IQANUS(x) \
(((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
#define G_FW_IQ_CMD_IQANUD(x) \
(((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
#define S_FW_IQ_CMD_IQANDSTINDEX 0
#define G_FW_IQ_CMD_IQANDSTINDEX(x) \
(((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
#define G_FW_IQ_CMD_IQDROPRSS(x) \
(((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
#define G_FW_IQ_CMD_IQGTSMODE(x) \
(((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
#define G_FW_IQ_CMD_IQPCIECH(x) \
(((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
#define G_FW_IQ_CMD_IQDCAEN(x) \
(((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
#define G_FW_IQ_CMD_IQDCACPU(x) \
(((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
#define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
(((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
#define G_FW_IQ_CMD_IQCPRIO(x) \
(((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
#define S_FW_IQ_CMD_IQESIZE 0
#define G_FW_IQ_CMD_IQESIZE(x) \
(((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
#define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \
(((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
#define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
(((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
#define G_FW_IQ_CMD_IQFLINTISCSIC(x) \
(((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
#define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
(((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
#define G_FW_IQ_CMD_FL0CACHELOCK(x) \
(((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
#define G_FW_IQ_CMD_FL0DBP(x) \
(((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
#define G_FW_IQ_CMD_FL0DATANS(x) \
(((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
#define G_FW_IQ_CMD_FL0DATARO(x) \
(((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
#define G_FW_IQ_CMD_FL0CONGCIF(x) \
(((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
#define G_FW_IQ_CMD_FL0ONCHIP(x) \
(((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
#define G_FW_IQ_CMD_FL0STATUSPGNS(x) \
(((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
#define G_FW_IQ_CMD_FL0STATUSPGRO(x) \
(((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
#define G_FW_IQ_CMD_FL0FETCHNS(x) \
(((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
#define G_FW_IQ_CMD_FL0FETCHRO(x) \
(((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
#define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
(((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
#define G_FW_IQ_CMD_FL0CPRIO(x) \
(((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
#define G_FW_IQ_CMD_FL0PADEN(x) \
(((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
#define G_FW_IQ_CMD_FL0PACKEN(x) \
(((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
#define S_FW_IQ_CMD_FL0CONGEN 0
#define G_FW_IQ_CMD_FL0CONGEN(x) \
(((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
#define G_FW_IQ_CMD_FL0DCAEN(x) \
(((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
#define G_FW_IQ_CMD_FL0DCACPU(x) \
(((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
#define G_FW_IQ_CMD_FL0FBMIN(x) \
(((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
#define G_FW_IQ_CMD_FL0FBMAX(x) \
(((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \
(((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
#define S_FW_IQ_CMD_FL0CIDXFTHRESH 0
#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \
(((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
#define G_FW_IQ_CMD_FL1CNGCHMAP(x) \
(((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
#define G_FW_IQ_CMD_FL1CACHELOCK(x) \
(((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
#define G_FW_IQ_CMD_FL1DBP(x) \
(((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
#define G_FW_IQ_CMD_FL1DATANS(x) \
(((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
#define G_FW_IQ_CMD_FL1DATARO(x) \
(((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
#define G_FW_IQ_CMD_FL1CONGCIF(x) \
(((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
#define G_FW_IQ_CMD_FL1ONCHIP(x) \
(((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
#define G_FW_IQ_CMD_FL1STATUSPGNS(x) \
(((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
#define G_FW_IQ_CMD_FL1STATUSPGRO(x) \
(((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
#define G_FW_IQ_CMD_FL1FETCHNS(x) \
(((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
#define G_FW_IQ_CMD_FL1FETCHRO(x) \
(((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
#define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \
(((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
#define G_FW_IQ_CMD_FL1CPRIO(x) \
(((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
#define G_FW_IQ_CMD_FL1PADEN(x) \
(((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
#define G_FW_IQ_CMD_FL1PACKEN(x) \
(((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
#define S_FW_IQ_CMD_FL1CONGEN 0
#define G_FW_IQ_CMD_FL1CONGEN(x) \
(((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
#define G_FW_IQ_CMD_FL1DCAEN(x) \
(((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
#define G_FW_IQ_CMD_FL1DCACPU(x) \
(((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
#define G_FW_IQ_CMD_FL1FBMIN(x) \
(((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
#define G_FW_IQ_CMD_FL1FBMAX(x) \
(((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \
(((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
#define S_FW_IQ_CMD_FL1CIDXFTHRESH 0
#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \
(((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
struct fw_eq_mngt_cmd {
};
#define G_FW_EQ_MNGT_CMD_PFN(x) \
(((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
#define S_FW_EQ_MNGT_CMD_VFN 0
#define G_FW_EQ_MNGT_CMD_VFN(x) \
(((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
#define G_FW_EQ_MNGT_CMD_ALLOC(x) \
(((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
#define G_FW_EQ_MNGT_CMD_FREE(x) \
(((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
#define G_FW_EQ_MNGT_CMD_MODIFY(x) \
(((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
#define G_FW_EQ_MNGT_CMD_EQSTART(x) \
(((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
#define G_FW_EQ_MNGT_CMD_EQSTOP(x) \
(((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
#define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \
(((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
#define S_FW_EQ_MNGT_CMD_EQID 0
#define G_FW_EQ_MNGT_CMD_EQID(x) \
(((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
#define S_FW_EQ_MNGT_CMD_PHYSEQID 0
#define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \
(((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
#define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \
(((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \
(((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \
(((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
#define G_FW_EQ_MNGT_CMD_FETCHNS(x) \
(((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
#define G_FW_EQ_MNGT_CMD_FETCHRO(x) \
(((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \
(((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
#define G_FW_EQ_MNGT_CMD_CPRIO(x) \
(((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
#define G_FW_EQ_MNGT_CMD_ONCHIP(x) \
(((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
#define G_FW_EQ_MNGT_CMD_PCIECHN(x) \
(((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
#define S_FW_EQ_MNGT_CMD_IQID 0
#define G_FW_EQ_MNGT_CMD_IQID(x) \
(((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
#define G_FW_EQ_MNGT_CMD_DCAEN(x) \
(((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
#define G_FW_EQ_MNGT_CMD_DCACPU(x) \
(((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
#define G_FW_EQ_MNGT_CMD_FBMIN(x) \
(((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
#define G_FW_EQ_MNGT_CMD_FBMAX(x) \
(((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \
(((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
#define S_FW_EQ_MNGT_CMD_EQSIZE 0
#define G_FW_EQ_MNGT_CMD_EQSIZE(x) \
(((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
struct fw_eq_eth_cmd {
};
#define G_FW_EQ_ETH_CMD_PFN(x) \
(((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
#define S_FW_EQ_ETH_CMD_VFN 0
#define G_FW_EQ_ETH_CMD_VFN(x) \
(((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
#define G_FW_EQ_ETH_CMD_ALLOC(x) \
(((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
#define G_FW_EQ_ETH_CMD_FREE(x) \
(((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
#define G_FW_EQ_ETH_CMD_MODIFY(x) \
(((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
#define G_FW_EQ_ETH_CMD_EQSTART(x) \
(((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
#define G_FW_EQ_ETH_CMD_EQSTOP(x) \
(((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
#define S_FW_EQ_ETH_CMD_EQID 0
#define G_FW_EQ_ETH_CMD_EQID(x) \
(((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
#define S_FW_EQ_ETH_CMD_PHYSEQID 0
#define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
(((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
#define G_FW_EQ_ETH_CMD_FETCHSZM(x) \
(((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
#define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \
(((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
#define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \
(((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
#define G_FW_EQ_ETH_CMD_FETCHNS(x) \
(((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
#define G_FW_EQ_ETH_CMD_FETCHRO(x) \
(((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
(((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
#define G_FW_EQ_ETH_CMD_CPRIO(x) \
(((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
#define G_FW_EQ_ETH_CMD_ONCHIP(x) \
(((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
#define G_FW_EQ_ETH_CMD_PCIECHN(x) \
(((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
#define S_FW_EQ_ETH_CMD_IQID 0
#define G_FW_EQ_ETH_CMD_IQID(x) \
(((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
#define G_FW_EQ_ETH_CMD_DCAEN(x) \
(((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
#define G_FW_EQ_ETH_CMD_DCACPU(x) \
(((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
#define G_FW_EQ_ETH_CMD_FBMIN(x) \
(((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
#define G_FW_EQ_ETH_CMD_FBMAX(x) \
(((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \
(((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
(((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
#define S_FW_EQ_ETH_CMD_EQSIZE 0
#define G_FW_EQ_ETH_CMD_EQSIZE(x) \
(((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
#define G_FW_EQ_ETH_CMD_VIID(x) \
(((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
struct fw_eq_ctrl_cmd {
};
#define G_FW_EQ_CTRL_CMD_PFN(x) \
(((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
#define S_FW_EQ_CTRL_CMD_VFN 0
#define G_FW_EQ_CTRL_CMD_VFN(x) \
(((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
#define G_FW_EQ_CTRL_CMD_ALLOC(x) \
(((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
#define G_FW_EQ_CTRL_CMD_FREE(x) \
(((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
#define G_FW_EQ_CTRL_CMD_MODIFY(x) \
(((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
#define G_FW_EQ_CTRL_CMD_EQSTART(x) \
(((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
#define G_FW_EQ_CTRL_CMD_EQSTOP(x) \
(((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
#define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \
(((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
#define S_FW_EQ_CTRL_CMD_EQID 0
#define G_FW_EQ_CTRL_CMD_EQID(x) \
(((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
#define S_FW_EQ_CTRL_CMD_PHYSEQID 0
#define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
(((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
#define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \
(((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \
(((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \
(((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
#define G_FW_EQ_CTRL_CMD_FETCHNS(x) \
(((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
#define G_FW_EQ_CTRL_CMD_FETCHRO(x) \
(((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \
(((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
#define G_FW_EQ_CTRL_CMD_CPRIO(x) \
(((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
#define G_FW_EQ_CTRL_CMD_ONCHIP(x) \
(((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
#define G_FW_EQ_CTRL_CMD_PCIECHN(x) \
(((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
#define S_FW_EQ_CTRL_CMD_IQID 0
#define G_FW_EQ_CTRL_CMD_IQID(x) \
(((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
#define G_FW_EQ_CTRL_CMD_DCAEN(x) \
(((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
#define G_FW_EQ_CTRL_CMD_DCACPU(x) \
(((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
#define G_FW_EQ_CTRL_CMD_FBMIN(x) \
(((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
#define G_FW_EQ_CTRL_CMD_FBMAX(x) \
(((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \
(((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
#define S_FW_EQ_CTRL_CMD_EQSIZE 0
#define G_FW_EQ_CTRL_CMD_EQSIZE(x) \
(((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
struct fw_eq_ofld_cmd {
};
#define G_FW_EQ_OFLD_CMD_PFN(x) \
(((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
#define S_FW_EQ_OFLD_CMD_VFN 0
#define G_FW_EQ_OFLD_CMD_VFN(x) \
(((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
#define G_FW_EQ_OFLD_CMD_ALLOC(x) \
(((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
#define G_FW_EQ_OFLD_CMD_FREE(x) \
(((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
#define G_FW_EQ_OFLD_CMD_MODIFY(x) \
(((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
#define G_FW_EQ_OFLD_CMD_EQSTART(x) \
(((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
#define G_FW_EQ_OFLD_CMD_EQSTOP(x) \
(((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
#define S_FW_EQ_OFLD_CMD_EQID 0
#define G_FW_EQ_OFLD_CMD_EQID(x) \
(((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
#define S_FW_EQ_OFLD_CMD_PHYSEQID 0
#define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \
(((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
#define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \
(((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \
(((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \
(((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
#define G_FW_EQ_OFLD_CMD_FETCHNS(x) \
(((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
#define G_FW_EQ_OFLD_CMD_FETCHRO(x) \
(((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \
(((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
#define G_FW_EQ_OFLD_CMD_CPRIO(x) \
(((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
#define G_FW_EQ_OFLD_CMD_ONCHIP(x) \
(((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
#define G_FW_EQ_OFLD_CMD_PCIECHN(x) \
(((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
#define S_FW_EQ_OFLD_CMD_IQID 0
#define G_FW_EQ_OFLD_CMD_IQID(x) \
(((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
#define G_FW_EQ_OFLD_CMD_DCAEN(x) \
(((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
#define G_FW_EQ_OFLD_CMD_DCACPU(x) \
(((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
#define G_FW_EQ_OFLD_CMD_FBMIN(x) \
(((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
#define G_FW_EQ_OFLD_CMD_FBMAX(x) \
(((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \
(((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
#define S_FW_EQ_OFLD_CMD_EQSIZE 0
#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \
(((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
/*
* Macros for VIID parsing:
* VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
*/
#define S_FW_VIID_VIN 0
enum fw_vi_func {
};
struct fw_vi_cmd {
};
#define S_FW_VI_CMD_VFN 0
#define G_FW_VI_CMD_ALLOC(x) \
(((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
#define S_FW_VI_CMD_VIID 0
#define G_FW_VI_CMD_PORTID(x) \
(((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
#define S_FW_VI_CMD_RSSSIZE 0
#define G_FW_VI_CMD_RSSSIZE(x) \
(((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
#define S_FW_VI_CMD_IDSIIQ 0
#define G_FW_VI_CMD_IDSIIQ(x) \
(((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
#define S_FW_VI_CMD_IDSEIQ 0
#define G_FW_VI_CMD_IDSEIQ(x) \
(((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
/* Special VI_MAC command index ids */
enum fw_vi_mac_smac {
};
enum fw_vi_mac_result {
};
struct fw_vi_mac_cmd {
union fw_vi_mac {
struct fw_vi_mac_exact {
struct fw_vi_mac_hash {
} hash;
} u;
};
#define S_FW_VI_MAC_CMD_VIID 0
#define G_FW_VI_MAC_CMD_VIID(x) \
(((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
#define G_FW_VI_MAC_CMD_FREEMACS(x) \
(((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
#define G_FW_VI_MAC_CMD_HASHVECEN(x) \
(((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN)
#define G_FW_VI_MAC_CMD_HASHUNIEN(x) \
(((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
#define G_FW_VI_MAC_CMD_VALID(x) \
(((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
#define G_FW_VI_MAC_CMD_PRIO(x) \
(((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
#define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
(((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
#define S_FW_VI_MAC_CMD_IDX 0
#define G_FW_VI_MAC_CMD_IDX(x) \
(((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
/* T4 max MTU supported */
struct fw_vi_rxmode_cmd {
};
#define S_FW_VI_RXMODE_CMD_VIID 0
#define G_FW_VI_RXMODE_CMD_VIID(x) \
(((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
#define G_FW_VI_RXMODE_CMD_MTU(x) \
(((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
(((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
(((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \
#define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
(((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
struct fw_vi_enable_cmd {
};
#define S_FW_VI_ENABLE_CMD_VIID 0
#define G_FW_VI_ENABLE_CMD_VIID(x) \
(((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
#define G_FW_VI_ENABLE_CMD_IEN(x) \
(((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
#define G_FW_VI_ENABLE_CMD_EEN(x) \
(((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
#define G_FW_VI_ENABLE_CMD_LED(x) \
(((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
/* VI VF stats offset definitions */
enum fw_vi_stats_vf_index {
};
/* VI PF stats offset definitions */
enum fw_vi_stats_pf_index {
};
struct fw_vi_stats_cmd {
union fw_vi_stats {
struct fw_vi_stats_ctl {
} ctl;
struct fw_vi_stats_pf {
} pf;
struct fw_vi_stats_vf {
} vf;
} u;
};
#define S_FW_VI_STATS_CMD_VIID 0
#define G_FW_VI_STATS_CMD_VIID(x) \
(((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
#define G_FW_VI_STATS_CMD_NSTATS(x) \
(((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
#define S_FW_VI_STATS_CMD_IX 0
#define G_FW_VI_STATS_CMD_IX(x) \
(((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
struct fw_acl_mac_cmd {
};
#define G_FW_ACL_MAC_CMD_PFN(x) \
(((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
#define S_FW_ACL_MAC_CMD_VFN 0
#define G_FW_ACL_MAC_CMD_VFN(x) \
(((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
#define G_FW_ACL_MAC_CMD_EN(x) \
(((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
struct fw_acl_vlan_cmd {
};
#define G_FW_ACL_VLAN_CMD_PFN(x) \
(((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
#define S_FW_ACL_VLAN_CMD_VFN 0
#define G_FW_ACL_VLAN_CMD_VFN(x) \
(((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
#define G_FW_ACL_VLAN_CMD_EN(x) \
(((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \
(((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
#define G_FW_ACL_VLAN_CMD_FM(x) \
(((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
/* port capabilities bitmap */
enum fw_port_cap {
};
#define G_FW_PORT_AUXLINFO_MDI(x) \
(((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI)
#define G_FW_PORT_AUXLINFO_KX4(x) \
(((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
#define G_FW_PORT_AUXLINFO_KR(x) \
(((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
#define S_FW_PORT_AUXLINFO_FEC 0
#define G_FW_PORT_AUXLINFO_FEC(x) \
(((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC)
#define G_FW_PORT_RCAP_AUX(x) \
(((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX)
#define S_FW_PORT_CAP_SPEED 0
#define G_FW_PORT_CAP_SPEED(x) \
(((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
#define G_FW_PORT_CAP_FC(x) \
(((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
#define G_FW_PORT_CAP_ANEG(x) \
(((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
enum fw_port_mdi {
};
enum fw_port_action {
};
enum fw_port_l2cfg_ctlbf {
};
enum fw_port_dcb_cfg {
};
enum fw_port_dcb_cfg_rc {
};
enum fw_port_dcb_type {
};
struct fw_port_cmd {
union fw_port {
struct fw_port_l1cfg {
__be32 r;
} l1cfg;
struct fw_port_l2cfg {
} l2cfg;
struct fw_port_info {
} info;
union fw_port_dcb {
struct fw_port_dcb_pgid {
} pgid;
struct fw_port_dcb_pgrate {
} pgrate;
struct fw_port_dcb_priorate {
} priorate;
struct fw_port_dcb_pfc {
} pfc;
struct fw_port_app_priority {
} app_priority;
} dcb;
} u;
};
#define G_FW_PORT_CMD_READ(x) \
(((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
#define S_FW_PORT_CMD_PORTID 0
#define G_FW_PORT_CMD_PORTID(x) \
(((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
#define G_FW_PORT_CMD_ACTION(x) \
(((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
#define G_FW_PORT_CMD_OVLAN3(x) \
(((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
#define G_FW_PORT_CMD_OVLAN2(x) \
(((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
#define G_FW_PORT_CMD_OVLAN1(x) \
(((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
#define G_FW_PORT_CMD_OVLAN0(x) \
(((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
#define G_FW_PORT_CMD_IVLAN0(x) \
(((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
#define G_FW_PORT_CMD_TXIPG(x) \
(((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
#define S_FW_PORT_CMD_FORCE_PINFO 0
#define G_FW_PORT_CMD_FORCE_PINFO(x) \
(((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
#define G_FW_PORT_CMD_LSTATUS(x) \
(((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
#define G_FW_PORT_CMD_LSPEED(x) \
(((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
#define G_FW_PORT_CMD_TXPAUSE(x) \
(((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
#define G_FW_PORT_CMD_RXPAUSE(x) \
(((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
#define G_FW_PORT_CMD_MDIOCAP(x) \
(((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
#define G_FW_PORT_CMD_MDIOADDR(x) \
(((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
#define G_FW_PORT_CMD_LPTXPAUSE(x) \
(((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
#define G_FW_PORT_CMD_LPRXPAUSE(x) \
(((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
#define G_FW_PORT_CMD_PTYPE(x) \
(((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
#define G_FW_PORT_CMD_LINKDNRC(x) \
(((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
#define S_FW_PORT_CMD_MODTYPE 0
#define G_FW_PORT_CMD_MODTYPE(x) \
(((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
#define G_FW_PORT_CMD_APPLY(x) \
(((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
/*
* These are configured into the VPD and hence tools that generate
* VPD may use this enumeration.
* extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
*/
enum fw_port_type {
/* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
/* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
};
/*
* These are read from module's EEPROM and determined once the module is
* inserted.
*/
enum fw_port_module_type {
};
/* used by FW and tools may use this to generate VPD */
enum fw_port_mod_sub_type {
/*
* The following will never been in the VPD. They are TWINAX cable
* lengths decoded from SFP+ module i2c PROMs. These should almost
* certainly go somewhere else ...
*/
};
/* link down reason codes (3b) */
enum fw_port_link_dn_rc {
};
/* port stats */
enum fw_port_stats_tx_index {
};
enum fw_port_stat_rx_index {
};
struct fw_port_stats_cmd {
union fw_port_stats {
struct fw_port_stats_ctl {
} ctl;
struct fw_port_stats_all {
} all;
} u;
};
#define G_FW_PORT_STATS_CMD_NSTATS(x) \
(((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
#define S_FW_PORT_STATS_CMD_BG_BM 0
#define G_FW_PORT_STATS_CMD_BG_BM(x) \
(((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
#define G_FW_PORT_STATS_CMD_TX(x) \
(((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
#define S_FW_PORT_STATS_CMD_IX 0
#define G_FW_PORT_STATS_CMD_IX(x) \
(((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
/* port loopback stats */
enum fw_port_lb_stats_index {
};
struct fw_port_lb_stats_cmd {
union fw_port_lb_stats {
struct fw_port_lb_stats_ctl {
} ctl;
struct fw_port_lb_stats_all {
} all;
} u;
};
#define S_FW_PORT_LB_STATS_CMD_LBPORT 0
#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
#define S_FW_PORT_LB_STATS_CMD_BG_BM 0
#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \
(((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
#define S_FW_PORT_LB_STATS_CMD_IX 0
#define G_FW_PORT_LB_STATS_CMD_IX(x) \
(((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
/* Trace related defines */
struct fw_port_trace_cmd {
};
#define S_FW_PORT_TRACE_CMD_PORTID 0
#define G_FW_PORT_TRACE_CMD_PORTID(x) \
(((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
#define G_FW_PORT_TRACE_CMD_TRACEEN(x) \
(((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
#define G_FW_PORT_TRACE_CMD_FLTMODE(x) \
(((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
#define G_FW_PORT_TRACE_CMD_DUPLEN(x) \
(((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
(((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
#define G_FW_PORT_TRACE_CMD_PCIECH(x) \
(((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
struct fw_port_trace_mmap_cmd {
};
#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0
#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \
#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
(((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
struct fw_rss_ind_tbl_cmd {
};
#define S_FW_RSS_IND_TBL_CMD_VIID 0
#define G_FW_RSS_IND_TBL_CMD_VIID(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
#define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
#define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
#define S_FW_RSS_IND_TBL_CMD_IQ2 0
#define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
#define G_FW_RSS_IND_TBL_CMD_IQ3(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
#define G_FW_RSS_IND_TBL_CMD_IQ4(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
#define S_FW_RSS_IND_TBL_CMD_IQ5 0
#define G_FW_RSS_IND_TBL_CMD_IQ5(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
#define G_FW_RSS_IND_TBL_CMD_IQ6(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
#define G_FW_RSS_IND_TBL_CMD_IQ7(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
#define S_FW_RSS_IND_TBL_CMD_IQ8 0
#define G_FW_RSS_IND_TBL_CMD_IQ8(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
#define G_FW_RSS_IND_TBL_CMD_IQ9(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
#define G_FW_RSS_IND_TBL_CMD_IQ10(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
#define S_FW_RSS_IND_TBL_CMD_IQ11 0
#define G_FW_RSS_IND_TBL_CMD_IQ11(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
#define G_FW_RSS_IND_TBL_CMD_IQ12(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
#define G_FW_RSS_IND_TBL_CMD_IQ13(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
#define S_FW_RSS_IND_TBL_CMD_IQ14 0
#define G_FW_RSS_IND_TBL_CMD_IQ14(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
#define G_FW_RSS_IND_TBL_CMD_IQ15(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
#define G_FW_RSS_IND_TBL_CMD_IQ16(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
#define S_FW_RSS_IND_TBL_CMD_IQ17 0
#define G_FW_RSS_IND_TBL_CMD_IQ17(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
#define G_FW_RSS_IND_TBL_CMD_IQ18(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
#define G_FW_RSS_IND_TBL_CMD_IQ19(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
#define S_FW_RSS_IND_TBL_CMD_IQ20 0
#define G_FW_RSS_IND_TBL_CMD_IQ20(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
#define G_FW_RSS_IND_TBL_CMD_IQ21(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
#define G_FW_RSS_IND_TBL_CMD_IQ22(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
#define S_FW_RSS_IND_TBL_CMD_IQ23 0
#define G_FW_RSS_IND_TBL_CMD_IQ23(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
#define G_FW_RSS_IND_TBL_CMD_IQ24(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
#define G_FW_RSS_IND_TBL_CMD_IQ25(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
#define S_FW_RSS_IND_TBL_CMD_IQ26 0
#define G_FW_RSS_IND_TBL_CMD_IQ26(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
#define G_FW_RSS_IND_TBL_CMD_IQ27(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
#define G_FW_RSS_IND_TBL_CMD_IQ28(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
#define S_FW_RSS_IND_TBL_CMD_IQ29 0
#define G_FW_RSS_IND_TBL_CMD_IQ29(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
#define G_FW_RSS_IND_TBL_CMD_IQ30(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
#define G_FW_RSS_IND_TBL_CMD_IQ31(x) \
(((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
struct fw_rss_glb_config_cmd {
union fw_rss_glb_config {
struct fw_rss_glb_config_manual {
} manual;
struct fw_rss_glb_config_basicvirtual {
} basicvirtual;
} u;
};
#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \
#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \
#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \
#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
struct fw_rss_vi_config_cmd {
union fw_rss_vi_config {
struct fw_rss_vi_config_manual {
} manual;
struct fw_rss_vi_config_basicvirtual {
} basicvirtual;
} u;
};
#define S_FW_RSS_VI_CONFIG_CMD_VIID 0
#define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
#define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
enum fw_sched_sc {
FW_SCHED_SC_CONFIG = 0,
};
enum fw_sched_type {
};
enum fw_sched_params_level {
};
enum fw_sched_params_mode {
};
enum fw_sched_params_unit {
};
enum fw_sched_params_rate {
};
struct fw_sched_cmd {
union fw_sched {
struct fw_sched_config {
} config;
struct fw_sched_params {
} params;
} u;
};
/*
* length of the formatting string
*/
/*
* maximum number of the formatting string parameters
*/
/*
* priority levels
*/
enum fw_devlog_level {
};
/*
* facilities that may send a log message
*/
enum fw_devlog_facility {
};
/*
* log message format
*/
struct fw_devlog_e {
};
struct fw_devlog_cmd {
};
#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
(((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & \
#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
(((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
enum fw_watchdog_actions {
};
struct fw_watchdog_cmd {
};
struct fw_clip_cmd {
};
#define G_FW_CLIP_CMD_ALLOC(x) \
(((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
#define G_FW_CLIP_CMD_FREE(x) \
(((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
/*
* ************************************
* F O i S C S I C O M M A N D s
* ************************************
*/
enum fw_chnet_iface_cmd_subop {
};
struct fw_chnet_iface_cmd {
};
#define S_FW_CHNET_IFACE_CMD_PORTID 0
#define G_FW_CHNET_IFACE_CMD_PORTID(x) \
(((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
#define G_FW_CHNET_IFACE_CMD_IFID(x) \
(((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
#define S_FW_CHNET_IFACE_CMD_IFSTATE 0
#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \
(((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
/*
* **********************************
* F O F C O E C O M M A N D s
* **********************************
*/
struct fw_fcoe_res_info_cmd {
};
struct fw_fcoe_link_cmd {
};
#define S_FW_FCOE_LINK_CMD_PORTID 0
#define G_FW_FCOE_LINK_CMD_PORTID(x) \
(((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
#define S_FW_FCOE_LINK_CMD_FCFI 0
#define G_FW_FCOE_LINK_CMD_FCFI(x) \
(((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
#define S_FW_FCOE_LINK_CMD_VNPI 0
#define G_FW_FCOE_LINK_CMD_VNPI(x) \
(((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
struct fw_fcoe_vnp_cmd {
};
#define S_FW_FCOE_VNP_CMD_FCFI 0
#define G_FW_FCOE_VNP_CMD_FCFI(x) \
(((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
#define G_FW_FCOE_VNP_CMD_ALLOC(x) \
(((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
#define G_FW_FCOE_VNP_CMD_FREE(x) \
(((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
#define G_FW_FCOE_VNP_CMD_MODIFY(x) \
(((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \
(((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
#define G_FW_FCOE_VNP_CMD_PERSIST(x) \
(((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \
(((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
#define S_FW_FCOE_VNP_CMD_VNPI 0
#define G_FW_FCOE_VNP_CMD_VNPI(x) \
(((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
struct fw_fcoe_sparams_cmd {
};
#define S_FW_FCOE_SPARAMS_CMD_PORTID 0
#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \
(((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
struct fw_fcoe_stats_cmd {
union fw_fcoe_stats {
struct fw_fcoe_stats_ctl {
} ctl;
struct fw_fcoe_port_stats {
} port_stats;
struct fw_fcoe_fcf_stats {
} fcf_stats;
struct fw_fcoe_pcb_stats {
} pcb_stats;
struct fw_fcoe_scb_stats {
} scb_stats;
} u;
};
#define S_FW_FCOE_STATS_CMD_FLOWID 0
#define G_FW_FCOE_STATS_CMD_FLOWID(x) \
(((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
#define G_FW_FCOE_STATS_CMD_FREE(x) \
(((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
#define G_FW_FCOE_STATS_CMD_NSTATS(x) \
(((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
#define S_FW_FCOE_STATS_CMD_PORT 0
#define G_FW_FCOE_STATS_CMD_PORT(x) \
(((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
(((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & \
#define S_FW_FCOE_STATS_CMD_IX 0
#define G_FW_FCOE_STATS_CMD_IX(x) \
(((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
struct fw_fcoe_fcf_cmd {
};
#define S_FW_FCOE_FCF_CMD_FCFI 0
#define G_FW_FCOE_FCF_CMD_FCFI(x) \
(((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
#define S_FW_FCOE_FCF_CMD_PRIORITY 0
#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \
(((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
#define G_FW_FCOE_FCF_CMD_FPMA(x) \
(((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
#define G_FW_FCOE_FCF_CMD_SPMA(x) \
(((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
#define G_FW_FCOE_FCF_CMD_LOGIN(x) \
(((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
#define S_FW_FCOE_FCF_CMD_PORTID 0
#define G_FW_FCOE_FCF_CMD_PORTID(x) \
(((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
/*
* ****************************************************
* E R R O R a n d D E B U G C O M M A N D s
* ****************************************************
*/
enum fw_error_type {
};
struct fw_error_cmd {
union fw_error {
struct fw_error_exception {
} exception;
struct fw_error_hwmodule {
} hwmodule;
struct fw_error_wr {
} wr;
struct fw_error_acl {
} acl;
} u;
};
#define G_FW_ERROR_CMD_FATAL(x) \
(((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
#define S_FW_ERROR_CMD_TYPE 0
#define G_FW_ERROR_CMD_TYPE(x) \
(((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
#define G_FW_ERROR_CMD_PFN(x) \
(((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
#define S_FW_ERROR_CMD_VFN 0
#define G_FW_ERROR_CMD_VFN(x) \
(((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
#define G_FW_ERROR_CMD_PFN(x) \
(((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
#define S_FW_ERROR_CMD_VFN 0
#define G_FW_ERROR_CMD_VFN(x) \
(((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
#define G_FW_ERROR_CMD_MV(x) \
(((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
struct fw_debug_cmd {
union fw_debug {
struct fw_debug_assert {
__be32 x;
__be32 y;
} assert;
struct fw_debug_prt {
} prt;
} u;
};
#define S_FW_DEBUG_CMD_TYPE 0
#define G_FW_DEBUG_CMD_TYPE(x) \
(((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
/*
* ************************************
* P C I E F W R E G I S T E R
* ************************************
*/
/*
* Register definitions for the PCIE_FW register which the firmware uses
* to restain status across RESETs. This register should be considered
* as a READ-ONLY register for Host Software and only to be used to
* track firmware initialization/error state, etc.
*/
#define V_PCIE_FW_ASYNCNOT_VLD(x) \
((x) << S_PCIE_FW_ASYNCNOT_VLD)
#define G_PCIE_FW_ASYNCNOT_VLD(x) \
(((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
#define V_PCIE_FW_ASYNCNOTINT(x) \
((x) << S_PCIE_FW_ASYNCNOTINT)
#define G_PCIE_FW_ASYNCNOTINT(x) \
(((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
#define G_PCIE_FW_ASYNCNOT(x) \
(((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
#define G_PCIE_FW_MASTER_VLD(x) \
(((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
#define G_PCIE_FW_RESET_VLD(x) \
(((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
#define G_PCIE_FW_RESET(x) \
(((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
#define S_PCIE_FW_REGISTERED 0
#define G_PCIE_FW_REGISTERED(x) \
(((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
/*
* ********************************************
* B I N A R Y H E A D E R F O R M A T
* ********************************************
*/
/*
* firmware binary header format
*/
struct fw_hdr {
};
enum fw_hdr_chip {
};
#define V_FW_HDR_FW_VER_MAJOR(x) \
((x) << S_FW_HDR_FW_VER_MAJOR)
#define G_FW_HDR_FW_VER_MAJOR(x) \
(((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
#define V_FW_HDR_FW_VER_MINOR(x) \
((x) << S_FW_HDR_FW_VER_MINOR)
#define G_FW_HDR_FW_VER_MINOR(x) \
(((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
#define V_FW_HDR_FW_VER_MICRO(x) \
((x) << S_FW_HDR_FW_VER_MICRO)
#define G_FW_HDR_FW_VER_MICRO(x) \
(((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
#define S_FW_HDR_FW_VER_BUILD 0
#define V_FW_HDR_FW_VER_BUILD(x) \
((x) << S_FW_HDR_FW_VER_BUILD)
#define G_FW_HDR_FW_VER_BUILD(x) \
(((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
enum fw_hdr_intfver {
};
enum fw_hdr_flags {
};
#endif /* _T4FW_INTERFACE_H_ */