/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
*/
/*
* This file is part of the Chelsio T4 support code.
*
* Copyright (C) 2003-2013 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
* release for licensing terms and conditions.
*/
/* This file is automatically generated --- changes will be lost */
#ifndef _T4_TCB_DEFS_H
#define _T4_TCB_DEFS_H
/* 3:0 */
#define W_TCB_ULP_TYPE 0
#define S_TCB_ULP_TYPE 0
/* 11:4 */
#define W_TCB_ULP_RAW 0
/* 23:12 */
#define W_TCB_L2T_IX 0
/* 31:24 */
#define W_TCB_SMAC_SEL 0
/* 95:32 */
#define S_TCB_T_FLAGS 0
/* 105:96 */
#define S_TCB_RSS_INFO 0
/* 111:106 */
/* 115:112 */
/* 119:116 */
/* 123:120 */
/* 127:124 */
/* 131:128 */
#define S_TCB_RCV_SCALE 0
/* 135:132 */
/* 139:136 */
/* 143:140 */
/* 159:144 */
/* 191:160 */
#define S_TCB_TIMESTAMP 0
/* 223:192 */
#define S_TCB_T_RTT_TS_RECENT_AGE 0
/* 255:224 */
#define S_TCB_T_RTSEQ_RECENT 0
/* 271:256 */
#define S_TCB_T_SRTT 0
/* 287:272 */
/* 319:288 */
#define S_TCB_TX_MAX 0
/* 347:320 */
#define S_TCB_SND_UNA_RAW 0
/* 375:348 */
/* 403:376 */
/* 431:404 */
/* 459:432 */
/* 487:460 */
/* 504:488 */
/* 521:505 */
/* 553:522 */
/* 581:554 */
/* 609:582 */
/* 637:610 */
/* 665:638 */
#define V_TCB_RX_FRAG0_START_IDX_RAW(x) \
((__u64)(x) << S_TCB_RX_FRAG0_START_IDX_RAW)
/* 693:666 */
#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) \
((__u64)(x) << S_TCB_RX_FRAG1_START_IDX_OFFSET)
/* 721:694 */
/* 749:722 */
/* 765:750 */
/* 782:766 */
/* 799:783 */
/* 831:800 */
#define S_TCB_MAIN_SLUSH 0
/* 846:832 */
#define S_TCB_AUX1_SLUSH0 0
/* 874:847 */
#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) \
((__u64)(x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW)
/* 891:875 */
/* 919:892 */
/* 936:920 */
/* 964:937 */
/* 992:965 */
#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) \
((__u64)(x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW)
/* 1000:993 */
/* 1023:1001 */
/* 840:832 */
#define S_TCB_IRS_ULP 0
/* 849:841 */
/* 863:850 */
/* 879:864 */
#define S_TCB_CQ_IDX_SQ 0
/* 895:880 */
/* 911:896 */
#define S_TCB_QP_ID 0
/* 927:912 */
/* 959:928 */
#define S_TCB_STAG 0
/* 985:960 */
#define S_TCB_RQ_START 0
/* 998:986 */
/* 1002:999 */
/* 1015:1003 */
/* 1019:1016 */
/* 1020:1020 */
/* 1021:1021 */
/* 1022:1022 */
/* 1023:1023 */
/* 855:832 */
#define S_TCB_RX_DDP_BUF0_OFFSET 0
/* 879:856 */
/* 903:880 */
/* 927:904 */
/* 951:928 */
#define S_TCB_RX_DDP_BUF1_LEN 0
/* 959:952 */
/* 991:960 */
#define S_TCB_RX_DDP_BUF0_TAG 0
/* 1023:992 */
#define S_TCB_RX_DDP_BUF1_TAG 0
#define S_TF_MIGRATING 0
#define V_TF_RCV_COALESCE_HEARTBEAT(x) \
((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT)
#define V_TF_DDP_PSH_NO_INVALIDATE1(x) \
((__u64)(x) << S_TF_DDP_PSH_NO_INVALIDATE1)
#endif /* _T4_TCB_DEFS_H */