/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
*/
/*
* This file is part of the Chelsio T4 support code.
*
* Copyright (C) 2003-2013 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
* release for licensing terms and conditions.
*/
/* This file was automatically generated --- changes will be lost */
#ifndef _CXGBE_T4_REGS_H
#define _CXGBE_T4_REGS_H
/* registers for module SGE */
#define S_PIDX 0
#define S_CIDXINC 0
#define S_GLOBALENABLE 0
#define S_HOSTPAGESIZEPF0 0
#define S_QUEUESPERPAGEPF0 0
#define G_QUEUESPERPAGEVFPF7(x) \
(((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
#define G_QUEUESPERPAGEVFPF6(x) \
(((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
#define G_QUEUESPERPAGEVFPF5(x) \
(((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
#define G_QUEUESPERPAGEVFPF4(x) \
(((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
#define G_QUEUESPERPAGEVFPF3(x) \
(((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
#define G_QUEUESPERPAGEVFPF2(x) \
(((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
#define G_QUEUESPERPAGEVFPF1(x) \
(((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
#define S_QUEUESPERPAGEVFPF0 0
#define G_QUEUESPERPAGEVFPF0(x) \
(((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
#define S_LENGTH_MAX 0
#define S_WR_ERROR_OPCODE 0
#define S_INJECTDATAERR 0
#define S_PERR_EGR_CTXT_MIFRSP 0
#define S_PERR_BASE_SIZE 0
#define S_ERR_INV_CTXT0 0
#define S_NOEDRAM 0
#define S_TP_ENABLE 0
#define S_TSVAL 0
#define S_THRESHOLD_3 0
#define S_LP_COUNT 0
#define S_DROPPED_DB 0
#define S_THROTTLE_ENABLE 0
#define S_LL_READ_WAIT_DISABLE 0
#define S_TIMERVALUE1 0
#define S_TIMERVALUE3 0
#define S_TIMERVALUE5 0
#define S_MAXRSPCNT1 0
#define S_MAXRSPCNT3 0
#define S_ERR_UNEXPECTED_TIMER 0
#define S_STATSOURCE 0
#define G_HINTSALLOWEDNOHDR(x) \
(((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
#define S_HINTSALLOWEDHDR 0
#define S_EDMA_WEIGHT 0
#define S_ERROR_QID 0
#define S_MINTAG0 0
#define S_TAGPOOLTOTAL 0
#define S_CTXTQID 0
#define G_INGRESS2_LOG2SIZE(x) \
(((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
#define S_INGRESS1_LOG2SIZE 0
#define G_INGRESS1_LOG2SIZE(x) \
(((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
#define S_INGRESS1_BASE 0
/* registers for module PCIE */
#define S_CLIDECEN 0
#define S_MSGTYPE 0
#define S_MSIADDRLPERR 0
#define S_IDE 0
#define S_CFGSNP 0
#define S_LINKDNRSTEN 0
#define S_MAXTAG 0
#define S_DMA_REQCNT 0
#define S_REQCNT 0
#define S_FORCEPROGRESSCNT 0
#define S_REGISTER 0
#define S_WINDOW 0
#define S_MBOXWIN 0
#define S_MA_MAXTAG 0
#define S_PIOPAUSE 0
#define S_PCIE_MAX_RDSIZE 0
#define S_SELECT 0
#define S_VECBASE 0
#define S_PFNUM 0
#define S_FUNC 0
#define S_CRMC 0
#define S_OP3H 0
#define S_OP3D 0
#define S_IP3H 0
#define S_IP3D 0
#define S_ON3H 0
#define S_IN3H 0
#define S_OC3T 0
#define S_IC3T 0
#define S_OPM7 0
#define S_PDEBUGSELL 0
#define S_CDEBUGSELL 0
#define S_CH0 0
#define S_CH0_SOP 0
#define S_CH0_WSOP 0
#define S_CH0_RSP_FREE 0
#define S_CH2_RSP_FREE 0
#define S_CMD_CH0_RSP_FREE 0
#define S_MAXBUFWRREQ 0
/* registers for module DBG */
#define S_CLKSELECT 0
#define S_DBG_PORTEN 0
#define S_GPIO0_OUT_VAL 0
#define S_GPIO0_IN 0
#define S_GPIO0 0
#define S_DEBUGDATA 0
#define S_OVERWRSERCFG_EN 0
#define S_C_OCLK_EN 0
#define S_PLL_C_LOCK 0
#define S_GPIO0_ACT_LOW 0
#define G_STATIC_U_PLL_MULT(x) \
(((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
#define G_STATIC_U_PLL_PREDIV(x) \
(((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
#define G_STATIC_U_PLL_RANGEA(x) \
(((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
#define G_STATIC_U_PLL_RANGEB(x) \
(((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
#define S_STATIC_U_PLL_TUNE 0
#define G_STATIC_U_PLL_TUNE(x) \
(((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
#define G_STATIC_C_PLL_MULT(x) \
(((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
#define G_STATIC_C_PLL_PREDIV(x) \
(((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
#define G_STATIC_C_PLL_RANGEA(x) \
(((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
#define G_STATIC_C_PLL_RANGEB(x) \
(((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
#define S_STATIC_C_PLL_TUNE 0
#define G_STATIC_C_PLL_TUNE(x) \
(((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
#define G_STATIC_M_PLL_MULT(x) \
(((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
#define G_STATIC_M_PLL_PREDIV(x) \
(((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
#define G_STATIC_M_PLL_RANGEA(x) \
(((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
#define G_STATIC_M_PLL_RANGEB(x) \
(((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
#define S_STATIC_M_PLL_TUNE 0
#define G_STATIC_M_PLL_TUNE(x) \
(((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
#define S_STATIC_KX_PLL_P 0
#define S_STATIC_KR_PLL_P 0
#define G_STATIC_LVDS_CLKOUT_SEL(x) \
(((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
#define G_STATIC_CCLK_FREQ_SEL(x) \
(((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
#define G_STATIC_UCLK_FREQ_SEL(x) \
(((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
#define S_PSRO_SEL 0
#define S_KR_OCLK_MUXSEL 0
#define S_COUNTER0 0
#define S_STATIC_REFCLK_PERIOD 0
#define G_STATIC_REFCLK_PERIOD(x) \
(((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
#define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) \
((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
#define S_DBG_OPERATE0_OR_1 0
#define S_RD_EN0 0
#define S_WR_POINTER_ADDR0 0
#define S_RESET_CALIBRATE 0
#define G_LAST_MEASUREMENT_SELECT(x) \
(((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
#define V_LAST_MEASUREMENT_RESULT_BANK_B(x) \
((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
#define G_LAST_MEASUREMENT_RESULT_BANK_B(x) \
(((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & \
#define S_LAST_MEASUREMENT_RESULT_BANK_A 0
#define V_LAST_MEASUREMENT_RESULT_BANK_A(x) \
((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
#define G_LAST_MEASUREMENT_RESULT_BANK_A(x) \
(((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & \
#define S_PVT_REG_DRVN_A 0
#define S_PVT_REG_DRVP_A 0
#define S_PVT_REG_TERMN_A 0
#define S_PVT_REG_TERMP_A 0
#define S_THRESHOLD_DRVN_MIN_SYNC 0
#define S_REG_IN_TERMP_A 0
#define S_REG_IN_TERMN_A 0
#define S_REG_IN_DRVP_A 0
#define S_REG_IN_DRVN_A 0
#define S_REG_OUT_TERMP_A 0
#define S_REG_OUT_TERMN_A 0
#define S_REG_OUT_DRVP_A 0
#define S_REG_OUT_DRVN_A 0
#define S_TERMP_A_HISTORY 0
#define S_TERMN_A_HISTORY 0
#define S_DRVP_A_HISTORY 0
#define S_DRVN_A_HISTORY 0
#define S_SAMPLE_WAIT_CLKS 0
/* registers for module MC */
#define S_HW_LOW_POWER_EN 0
#define S_STATE_CMD 0
#define S_CTL_STAT 0
#define S_CMD_OPCODE 0
#define S_POWER_UP_START 0
#define S_POWER_UP_DONE 0
#define S_MEM_BL 0
#define S_PPMEM_EN 0
#define S_POWER_DOWN 0
#define S_RANK0_ODT_READ_NSEL 0
#define S_QSE_ALEN 0
#define S_DTU_ERR_B0 0
#define S_DTU_ALLBITS_0 0
#define S_DTU_ALLBITS_2 0
#define S_DTU_ALLBITS_4 0
#define S_DTU_ALLBITS_6 0
#define S_COLUMN_ADDR_WIDTH 0
#define G_COLUMN_ADDR_WIDTH(x) \
(((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
#define S_TOGGLE_COUNTER_1U 0
#define G_TOGGLE_COUNTER_1U(x) \
(((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
#define S_T_INIT 0
#define S_T_RSTH 0
#define S_TOGGLE_COUNTER_100N 0
#define G_TOGGLE_COUNTER_100N(x) \
(((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
#define S_T_REFI 0
#define S_T_MRD 0
#define S_T_RFC 0
#define S_T_RP 0
#define S_T_RTW 0
#define S_T_AL 0
#define S_T_CL 0
#define S_T_CWL 0
#define S_T_RAS 0
#define S_T_RC 0
#define S_T_RCD 0
#define S_T_RRD 0
#define S_T_RTP 0
#define S_T_WR 0
#define S_T_WTR 0
#define S_T_EXSR 0
#define S_T_XP 0
#define S_T_XPDLL 0
#define S_T_ZQCS 0
#define S_T_ZQCSI 0
#define S_T_DQS 0
#define S_T_CKSRE 0
#define S_T_CKSRX 0
#define S_T_CKE 0
#define S_T_MOD 0
#define S_RSTHOLD 0
#define S_T_ZQCL 0
#define S_T_ADWL_VEC 0
#define S_ECC_TEST_MASK 0
#define S_CLR_ECC_INTR 0
#define S_DTU_WR_COL 0
#define S_DTU_RD_COL 0
#define G_DTU_ROW_INCREMENTS(x) \
(((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
#define S_DTU_ENABLE 0
#define S_RUN_DTU 0
#define S_DTU_WR_BYTE0 0
#define S_DTU_WR_BYTE4 0
#define S_DTU_WR_BYTE8 0
#define S_DTU_WR_BYTE12 0
#define S_DM_WR_BYTE0 0
#define S_DTU_RD_BYTE0 0
#define S_DTU_RD_BYTE4 0
#define S_DTU_RD_BYTE8 0
#define S_DTU_RD_BYTE12 0
#define S_EA_COLUMN 0
#define G_PVT_UPD_DONE_TYPE(x) \
(((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
#define S_PHY_UPD_DONE_TYPE 0
#define G_PHY_UPD_DONE_TYPE(x) \
(((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
#define S_I_PHY_UPD_DONE 0
#define S_PHY_T_UPDON 0
#define S_PHY_T_UPDDLY 0
#define S_PVT_T_UPDON 0
#define S_PVT_T_UPDDLY 0
#define S_PHYPVT_T_UPDI 0
#define S_SOC_ODT_EN 0
#define S_PHY_T_UPDWAIT 0
#define S_PVT_T_UPDWAIT 0
#define S_MDLEN 0
#define S_CKOEN 0
#define S_CK4OEN 0
#define S_ACCAL 0
#define S_WLINC 0
#define S_PRD 0
#define S_DFLTDLY 0
#define S_CKINV 0
#define S_PSCALE 0
#define S_PHYRST 0
#define S_TESTA 0
#define S_TESTD 0
#define S_DDRCLKEN 0
#define S_WLSDVT 0
#define S_WDSDR_DLY 0
#define S_WL_DLY 0
#define S_DLY 0
#define S_MAXDLY 0
#define S_RDSDR_DLY 0
#define S_DP_DLY 0
#define S_RDQSCAL 0
#define S_DSINV 0
#define S_RANK 0
#define S_PHY_RST_N 0
#define S_RMW_PERF_CTRL 0
#define S_ECC_DISABLE 0
#define S_PERR_BLK_INT_ENABLE 0
#define S_RDATA_FIFOR_PAR_CAUSE 0
#define S_PERR_INT_ENABLE 0
#define S_PERR_INT_CAUSE 0
#define S_ECC_UECNT 0
#define S_CTLPHYRR 0
#define S_STATIC_SLOW 0
#define S_PCTL_ACCESS_STAT 0
#define S_RDATA_OCNT 0
#define S_BIST_OPCODE 0
#define S_BIST_DATA_TYPE 0
#define S_USER_DATA2 0
/* registers for module MA */
#define S_THRESHOLD0_EN 0
#define G_DBG_READ_DATA_CNT(x) \
(((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
#define G_DBG_WRITE_DATA_CNT(x) \
(((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
#define S_DBG_WRITE_REQ_CNT 0
#define G_DBG_WRITE_REQ_CNT(x) \
(((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
#define S_EDRAM0_SIZE 0
#define S_EDRAM1_SIZE 0
#define S_EXT_MEM_SIZE 0
#define S_HMA_SIZE 0
#define S_EXT_MEM_PAGE_SIZE 0
#define G_EXT_MEM_PAGE_SIZE(x) \
(((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
#define S_DIS_ADV_ARB 0
#define S_EDRAM0_ENABLE 0
#define S_MEM_WRAP_INT_ENABLE 0
#define S_MEM_WRAP_INT_CAUSE 0
#define S_MEM_WRAP_CLIENT_NUM 0
#define G_MEM_WRAP_CLIENT_NUM(x) \
(((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
#define S_TP_THREAD1_EN 0
#define S_SGE_THREAD1_EN 0
#define S_CL0_PAR_RDQUEUE_ERROR_EN 0
#define S_CL0_PAR_RDQUEUE_ERROR 0
#define G_COHERANCY_CMD_TYPE(x) \
(((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
#define G_COHERANCY_THREAD_NUM(x) \
(((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
#define S_COHERANCY_ENABLE 0
#define S_UE_ENABLE 0
/* registers for module EDC_0 */
#define S_REFFREQ 0
/* registers for module EDC_1 */
/* registers for module HMA */
/* registers for module CIM */
#define S_MBVFREADY 0
#define S_MBOWNER 0
#define S_UPCRST 0
#define S_UPSPAREINT 0
#define S_UPACCNONZERO 0
#define S_RSVDSPACEINTEN 0
#define S_RSVDSPACEINT 0
#define S_QUENUMSELECT 0
#define S_QUEFULLTHRSH 0
#define S_HOSTADDR 0
#define S_CDEBUGDATAL 0
#define S_IBQDBGEN 0
#define S_OBQDBGEN 0
#define S_DEBUGSELL 0
#define S_PILADBGWRPTR 0
#define S_ZONE_DST 0
#define S_GLBLTTICK 0
#define S_DPIFHOSTMASK 0
#define S_DPIFHUPAMASK 0
#define S_DUPMASK 0
#define S_DUPUACCMASK 0
#define S_PERREN 0
#define S_EEPROMBUSY 0
#define S_MA_TIMER_ENABLE 0
#define S_UP_PO_SINGLE_OUTSTANDING 0
/* registers for module TP */
#define S_CTUNNEL 0
#define S_CETHERNET 0
#define S_IPTTL 0
#define S_RXMAXOPCNT 0
#define S_TXPOOLSIZE 0
#define S_PMRXMAXPAGE 0
#define S_PMTXMAXPAGE 0
#define S_TIMESTAMPSMODE 0
#define S_MODE 0
#define S_TXDATAACKPAGEENABLE 0
#define S_ENABLETNLOFDCLOSED 0
#define G_TIMERBACKOFFINDEX3(x) \
(((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
#define G_TIMERBACKOFFINDEX2(x) \
(((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
#define G_TIMERBACKOFFINDEX1(x) \
(((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
#define S_TIMERBACKOFFINDEX0 0
#define G_TIMERBACKOFFINDEX0(x) \
(((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
#define G_TIMERBACKOFFINDEX7(x) \
(((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
#define G_TIMERBACKOFFINDEX6(x) \
(((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
#define G_TIMERBACKOFFINDEX5(x) \
(((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
#define S_TIMERBACKOFFINDEX4 0
#define G_TIMERBACKOFFINDEX4(x) \
(((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
#define G_TIMERBACKOFFINDEX11(x) \
(((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
#define G_TIMERBACKOFFINDEX10(x) \
(((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
#define G_TIMERBACKOFFINDEX9(x) \
(((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
#define S_TIMERBACKOFFINDEX8 0
#define G_TIMERBACKOFFINDEX8(x) \
(((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
#define G_TIMERBACKOFFINDEX15(x) \
(((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
#define G_TIMERBACKOFFINDEX14(x) \
(((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
#define G_TIMERBACKOFFINDEX13(x) \
(((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
#define S_TIMERBACKOFFINDEX12 0
#define G_TIMERBACKOFFINDEX12(x) \
(((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
#define S_SWSTIMER 0
#define S_INITIALSSTHRESH 0
#define S_RXCOALESCESIZE 0
#define S_RXCOALESCEPSHEN 0
#define S_RENOCFG 0
#define S_PUSHTIMERENABLE 0
#define S_DISABLEPDUXMT 0
#define S_PMMAXXFERLEN0 0
#define G_TABLELATENCYSTART(x) \
(((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
#define G_ENGINELATENCYDELTA(x) \
(((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
#define G_ENGINELATENCYMMGR(x) \
(((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
#define G_ENGINELATENCYWIREIP6(x) \
(((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
#define G_ENGINELATENCYWIRE(x) \
(((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
#define S_ENGINELATENCYBASE 0
#define G_ENGINELATENCYBASE(x) \
(((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
#define S_DROPERRORANY 0
#define G_TIMESTAMPRESOLUTION(x) \
(((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
#define S_DELAYEDACKRESOLUTION 0
#define G_DELAYEDACKRESOLUTION(x) \
(((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
#define S_MSL 0
#define S_RXTMIN 0
#define S_RXTMAX 0
#define S_PERSMIN 0
#define S_PERSMAX 0
#define S_KEEPALIVEIDLE 0
#define S_KEEPALIVEINTVL 0
#define S_INITSRTT 0
#define S_DACKTIME 0
#define S_FINWAIT2TIME 0
#define S_FASTFINWAIT2TIME 0
#define G_PERSHIFTBACKOFFMAX(x) \
(((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
#define S_KEEPALIVEMAXR2 0
#define S_CMTIMERMAXNUM 0
#define S_PORT0MTUVALUE 0
#define S_PORT2MTUVALUE 0
#define S_ROWVALUE 0
#define S_MTUVALUE 0
#define S_ULPTYPE0FIELD 0
#define S_LKPTBLQUEUE0 0
#define S_DISABLE 0
#define S_USEWIRECH 0
#define S_KEYWRADDR 0
#define S_QUEUE 0
#define S_VIRTPORT0TABLE 0
#define S_VIRTPORT2TABLE 0
#define S_TXCHANNELXOFFEN 0
#define S_TX_MOD_QUEUE_REQ_MAP 0
#define G_TX_MOD_QUEUE_REQ_MAP(x) \
(((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
#define S_TX_MODQ_WEIGHT4 0
#define S_TX_MODQ_WEIGHT0 0
#define G_RX_MOD_RATE_LIMIT_INC(x) \
(((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
#define G_RX_MOD_RATE_LIMIT_TICK(x) \
(((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
#define G_TX_MOD_RATE_LIMIT_INC(x) \
(((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
#define S_TX_MOD_RATE_LIMIT_TICK 0
#define G_TX_MOD_RATE_LIMIT_TICK(x) \
(((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
#define S_TPRESET 0
#define S_CMMAXPSTRUCT 0
#define S_DELINVFIFOPERR 0
#define S_FREEPSTRUCTCOUNT 0
#define S_FREERXPAGECOUNT 0
#define S_FREETXPAGECOUNT 0
#define S_DISABLETIMEFREEZE 0
#define S_TXRCVADVLTMSS 0
#define S_COMMITLIMIT0 0
#define S_RXMODXOFF0 0
#define S_OFDRATE0 0
#define S_TNLRATE0 0
#define S_DBGLARPTR 0
#define S_REQUESTDONE 0
#define S_PROTOCOLDATAFIELD 0
#define G_PROTOCOLDATAFIELD(x) \
(((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
#define S_TXTIMERSEPQ6 0
#define S_TXTIMERSEPQ4 0
#define S_TXTIMERSEPQ2 0
#define S_TXTIMERSEPQ0 0
#define S_RXTIMERSEPQ0 0
#define S_TXRATETCKQ6 0
#define S_TXRATETCKQ4 0
#define S_TXRATETCKQ2 0
#define S_TXRATETCKQ0 0
#define S_RXRATETCKQ0 0
#define S_RXMAPCHANNEL0 0
#define S_RXSGECHANNEL0 0
#define S_TXMAPCHANNEL0 0
#define S_TXMAPHDRCHANNEL0 0
#define G_TXMAPFIFOCHANNEL7(x) \
(((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
#define G_TXMAPFIFOCHANNEL6(x) \
(((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
#define G_TXMAPFIFOCHANNEL5(x) \
(((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
#define G_TXMAPFIFOCHANNEL4(x) \
(((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
#define G_TXMAPFIFOCHANNEL3(x) \
(((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
#define G_TXMAPFIFOCHANNEL2(x) \
(((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
#define G_TXMAPFIFOCHANNEL1(x) \
(((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
#define S_TXMAPFIFOCHANNEL0 0
#define G_TXMAPFIFOCHANNEL0(x) \
(((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
#define G_TXMAPPCMDCHANNEL7(x) \
(((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
#define G_TXMAPPCMDCHANNEL6(x) \
(((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
#define G_TXMAPPCMDCHANNEL5(x) \
(((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
#define G_TXMAPPCMDCHANNEL4(x) \
(((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
#define G_TXMAPPCMDCHANNEL3(x) \
(((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
#define G_TXMAPPCMDCHANNEL2(x) \
(((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
#define G_TXMAPPCMDCHANNEL1(x) \
(((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
#define S_TXMAPPCMDCHANNEL0 0
#define G_TXMAPPCMDCHANNEL0(x) \
(((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
#define G_TXMAPLPBKCHANNEL7(x) \
(((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
#define G_TXMAPLPBKCHANNEL6(x) \
(((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
#define G_TXMAPLPBKCHANNEL5(x) \
(((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
#define G_TXMAPLPBKCHANNEL4(x) \
(((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
#define G_TXMAPLPBKCHANNEL3(x) \
(((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
#define G_TXMAPLPBKCHANNEL2(x) \
(((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
#define G_TXMAPLPBKCHANNEL1(x) \
(((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
#define S_TXMAPLPBKCHANNEL0 0
#define G_TXMAPLPBKCHANNEL0(x) \
(((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
#define S_RXMAPE2CCHANNEL0 0
#define S_TXPPPENPORT0 0
#define S_IPMI_VLAN 0
#define S_PRIMARYPORT 0
#define S_CH0DEFAULTQUEUE 0
#define S_PF0LKPIDX 0
#define S_PF0MSKSIZE 0
#define S_KEYINDEX 0
#define S_VLANTYPE 0
#define S_IPV4TYPE 0
#define S_E_TCP_OPT_RXVALID 0
#define S_E_TCP_OPT_RXFULL 0
#define S_CPCMDEOICNT 0
#define S_EPLDTXZEROPDRDY 0
#define S_TIDVALUE 0
#define S_EPCMDBUSY 0
#define G_TABLEACCESSLATENCY(x) \
(((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
#define S_RCFDATACMRDY 0
#define S_RCFREASONOUT 0
#define S_EPCMDLENSAVE 0
#define S_TXMODXOFF 0
#define S_RXMODXOFF 0
#define S_PACKETDROPS 0
#define S_TXDROPCNTCH0RCVD 0
#define S_TXDROPCNTCH1RCVD 0
#define S_TXDROPMODECH0 0
#define S_ERXPLDEOPCNT 0
#define S_ERXFULL0 0
#define S_ERXFULL2 0
#define S_TXFULL 0
#define S_MAPWRITE 0
#define S_MAPVALUERD 0
#define S_CPLEOPCNT 0
#define S_FCOE 0
#define S_IPV6_EXT_HDR_SKIP 0
#define G_IPV6_EXT_HDR_SKIP(x) \
(((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
#define S_REWRITEFORCETOSIZE 0
#define S_TCPLIMIT 0
#define S_TCPOPTTXFULL 0
#define G_ERXPKTATTRFIFOFDONE(x) \
(((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
#define S_ETCPOPDONE 0
#define S_RX_PKT_ATTR_DRDY 0
#define S_ERXSIZEERROR0 0
#define S_RXDROP0 0
#define S_ETXFULL 0
#define S_SVID_ID_OFFSET 0
#define S_CRXCPLEOPCNT 0
#define S_TXCPLEOPCNT 0
#define S_CPL5_TXFULL0 0
#define S_CPL5_TXFULL2 0
#define S_DDPMSGLATEST0 0
#define S_CPRSERROR 0
#define S_PLD2X_TXAFULL 0
#define S_CH0LOW 0
#define S_CH0FIFOLIMIT 0
#define S_WRITEZEROOP 0
#define S_TRCCH 0
#define S_CPRSSTATE0 0
#define S_CTXPKTCSUMDONE 0
#define S_STROBE0 0
/* registers for module ULP_TX */
#define S_EXTRA_TAG_INSERTION_ENABLE 0
#define S_IMM_DATA_PERR_SET_CH0 0
#define S_CH0SIZE1 0
#define S_CH0SIZE2 0
#define S_ERR_CNT0 0
#define S_ERR_CNT1 0
#define S_ERR_CNT2 0
#define S_ERR_CNT3 0
#define S_ERR_CH0 0
#define S_CLR_CH0 0
#define S_EOP_CNT_CIM2ULP 0
#define S_DROP_CH0 0
/* registers for module PM_RX */
#define S_PREFETCH_ENABLE 0
#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
#define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
#define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) \
((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR \
#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) \
((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR \
#define S_E_PCMD_PAR_ERROR 0
/* registers for module PM_TX */
#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
#define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
#define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) \
((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) \
((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR \
#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) \
((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR \
#define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) \
((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR \
#define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) \
((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
#define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR \
#define S_C_PCMD_PAR_ERROR 0
/* registers for module MPS */
#define S_TIMEUNIT 0
#define S_RXSENDEN 0
#define S_XOFFDISABLE 0
#define S_RXHALTEN 0
#define S_RXSENDING 0
#define S_RXHALTED 0
#define S_ADDR 0
#define S_PRTY0 0
#define S_OVLAN_EN0 0
#define S_IVLAN_ETYPE 0
#define S_OVLAN_ETYPE 0
#define S_QUE_NUM 0
#define S_FIXED_VF 0
#define S_CREDIT 0
#define S_MAXPKTCNT 0
#define S_VF 0
#define S_RXEN 0
#define S_TAG 0
#define S_PF_VLAN_SEL 0
#define S_NUMPORTS 0
#define S_PLINTENB 0
#define S_PLINT 0
#define S_VALUE 0
#define S_WEIGHT 0
#define S_WOL_MODE 0
#define S_CH_MAP0 0
#define S_DBGSEL_L 0
#define S_OVLANSELMAC0 0
#define S_NCSI_SOURCE 0
#define S_TPFIFO 0
#define S_SECNT 0
#define S_PT0 0
#define S_DROPEN 0
#define S_DATACH0 0
#define S_DATACH2 0
#define S_DATAPT0 0
#define S_DATAPT2 0
#define S_SGEPAUSEIGNR 0
#define S_PORTL 0
#define S_LPBKERRSTAT 0
#define S_PLREADSYNCERR 0
#define S_TXPORT 0
#define S_DROP 0
#define S_MAC 0
#define S_TRCMULTIFILTER 0
#define S_QUEUENUMBER 0
#define S_TFOFFSET 0
#define S_TFCAPTUREMAX 0
#define S_TFRUNTSIZE 0
#define S_TFDROPBUFFERCOUNT 0
#define G_TFDROPBUFFERCOUNT(x) \
(((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
#define S_FILTMEM 0
#define S_VLANCLSEN 0
#define S_LPBKWEIGHT 0
#define S_MATCHSRAM 0
#define S_CLS_MATCH 0
#define S_PLTESTCTL 0
#define S_PRTBMCCTL 0
#define G_MACPARITYMASKSIZE(x) \
(((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
#define S_PORTMAP 0
#define S_TCAMYH 0
#define S_TCAMXH 0
#define S_SNF 0
#define S_CTL_P0 0
#define S_CNT 0
#define S_ALLOC 0
#define S_BORW 0
#define S_SHR_USED 0
#define S_TH 0
#define S_STOP 0
#define S_THRESH 0
#define S_GAP 0
#define S_CDM0 0
#define S_PG_TH_INT0 0
#define S_TH_LOW 0
#define S_OPCODE 0
#define S_DA 0
#define S_MAC_WT 0
#define S_OUTEN 0
#define S_MTU 0
#define S_PFVF 0
#define S_VLAN_ID 0
#define S_RPLC_MAP_ADDR 0
#define S_PF_EN 0
#define S_RX_SE_ERRMAP 0
#define S_EOP_CNT_IN 0
#define S_EOP_CNT_0 0
#define S_EOP_CNT_2 0
#define S_SPIERR 0
#define S_ST0 0
#define S_ST_TP 0
#define S_IN_DBG_CHNL 0
#define S_MAC_CNT0 0
#define S_MAC_CNT1 0
#define S_MAC_CNT2 0
#define S_MAC_CNT3 0
/* registers for module CPL_SWITCH */
#define S_CIM_ENABLE 0
#define S_SWITCH_TBL_IDX 0
#define S_ZERO_CMD_CH0 0
#define S_ZERO_SWITCH_ERROR 0
#define S_MAP_TBL_IDX 0
#define S_MAP_TBL_DATA 0
/* registers for module SMB */
#define S_MICROCNTCFG 0
#define S_MSTTIMEOUTCFG 0
#define S_MSTCTLEN 0
#define S_MSTBUSYSTS 0
#define S_SLVTIMEOUTCFG 0
#define S_SLVCTLEN 0
#define S_SLVBUSYSTS 0
#define S_MSTDONEINTEN 0
#define S_MSTDONEINT 0
#define S_DEBUGDATAL 0
#define S_SLVFIFOPERREN 0
#define S_FIFOINJDATAERREN 0
#define S_ARPADDRVAL 0
#define G_SUBSYSTEMVENDORID(x) \
(((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
#define S_SUBSYSTEMDEVICEID 0
#define G_SUBSYSTEMDEVICEID(x) \
(((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
#define S_INTERFACE 0
#define S_VENDORID 0
#define S_AUXADDR0 0
#define S_AUXADDR1 0
#define S_AUXADDR2 0
#define S_AUXADDR3 0
#define S_SMBUSCOMMANDCODE0 0
#define G_SMBUSCOMMANDCODE0(x) \
(((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
#define S_SMBUSCOMMANDCODE1 0
#define G_SMBUSCOMMANDCODE1(x) \
(((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
#define S_SMBUSCOMMANDCODE2 0
#define G_SMBUSCOMMANDCODE2(x) \
(((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
#define S_SMBUSCOMMANDCODE3 0
#define G_SMBUSCOMMANDCODE3(x) \
(((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
#define S_SMBUSCOMMANDCODE4 0
#define G_SMBUSCOMMANDCODE4(x) \
(((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
#define S_SMBUSCOMMANDCODE5 0
#define G_SMBUSCOMMANDCODE5(x) \
(((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
#define S_SMBUSCOMMANDCODE6 0
#define G_SMBUSCOMMANDCODE6(x) \
(((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
#define S_SMBUSCOMMANDCODE7 0
#define G_SMBUSCOMMANDCODE7(x) \
(((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
#define S_MICROCNTCLKCFG 0
/* registers for module I2CM */
#define S_I2C_CLKDIV 0
#define S_I2C_DATA 0
#define S_OP 0
/* registers for module MI */
#define S_MDIO_1P2V_SEL 0
#define S_REGADDR 0
#define S_MDIDATA 0
#define S_MDIOP 0
/* registers for module UART */
#define S_UART_CLKDIV 0
/* registers for module PMU */
#define S_INITPOWERMODE 0
#define S_WAKEUP 0
/* registers for module ULP_RX */
#define G_RDMA_0B_WR_OPCODE(x) \
(((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
#define S_TDDPTAGTCB 0
#define S_ENABLE_PRSDF_0 0
#define S_CAUSE_PRSDF_0 0
#define S_HPZ0 0
#define S_ULPRX_TID 0
#define S_CLRCHAN1 0
#define S_EOP_CNT_IN0 0
#define S_EOP_CNT_IN1 0
#define S_SEL_L 0
#define S_CHNL_SEL 0
#define S_TRC_SEL 0
#define S_RD_PTR 0
#define S_WR_PTR 0
/* registers for module SF */
/* registers for module PL */
#define S_VFID 0
#define S_PFMPS 0
#define S_SWINT 0
#define S_CIM 0
#define S_MAPDEFAULT 0
#define S_MAPXGMAC0 0
#define S_MAPXGMAC_KR0 0
#define S_MAPSMB 0
#define S_MAPI2CM 0
#define S_PIORSTMODE 0
#define S_PERRVFID 0
#define S_REV 0
#define S_ENABLEPF 0
#define S_SEMSRCPF 0
#define S_PF_ENABLE 0
#define S_MAP0 0
#define S_SLICEBASEADDR 0
#define S_MODOFFSET 0
#define S_FLR_PF 0
#define S_PL_TIMEOUT 0
#define S_PL_TORID 0
/* registers for module LE */
#define S_CMDOVERLAPDIS 0
#define S_CMPUNVAIL 0
#define S_ACTCNTIPV4 0
#define S_ACTCNTIPV6 0
#define S_HASHSIZE 0
#define S_SERVERHIT 0
#define S_INTTID 0
#define S_INTPTID 0
#define S_INTINDEX 0
#define S_INTCMD 0
#define S_DBGICMDMODE 0
#define S_DBGITINDEX 0
#define S_TCAM 0
#define S_DBGIRSPVALID 0
#define S_LASTCMDA 0
#define S_DROPFILTERFIDX 0
/* registers for module NCSI */
#define S_MAC_TX_RST 0
#define S_CH0_SADDR_HIGH 0
#define S_CH1_SADDR_HIGH 0
#define S_CH2_SADDR_HIGH 0
#define S_CH3_SADDR_HIGH 0
#define S_FWD_BMC 0
#define S_NCSI_ETHERTYPE 0
#define S_NCSI_RXFIFO_CNT 0
#define S_MPS2BMC_CNT 0
#define S_CIM2BMC_CNT 0
#define S_TX_FIFO_CNT 0
#define S_SE_CNT_CLR 0
#define S_MPS2NC_EOP_CNT 0
#define S_CIM2NC_EOP_CNT 0
#define G_BUS_STATE_MPS_OUT(x) \
(((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
#define G_BUS_STATE_CIM_OUT(x) \
(((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
#define S_BUS_STATE_CIM_IN 0
#define S_RXFIFO_PRTY_ERR 0
#define S_ARB_STATUS 0
#define S_FORCEPAUSE 0
#define S_PAUSELWM 0
#define S_DEBUGSEL 0
#define S_LOOPPHY 0
#define S_SPEED 0
#define S_LINKSTATUS 0
#define S_USEDBITREAD 0
#define S_NORXBUF 0
#define S_MGMTFRAMESENT 0
#define S_PAUSETIME 0
#define S_PAUSEFRRCVD 0
#define S_TXFRAMESOK 0
#define S_SINGLECOLTXFRAMES 0
#define G_SINGLECOLTXFRAMES(x) \
(((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
#define S_MULCOLTXFRAMES 0
#define S_RXFRAMESOK 0
#define S_RXFCSERR 0
#define S_RXALIGNERR 0
#define S_TXDEFERREDFRAMES 0
#define S_LATECOLLISIONS 0
#define S_EXCESSIVECOLLISIONS 0
#define G_EXCESSIVECOLLISIONS(x) \
(((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
#define S_TXUNDERRUNERR 0
#define S_CARRIERSENSEERRS 0
#define S_RXRESOURCEERR 0
#define S_RXOVERRUNERRCNT 0
#define S_RXSYMBOLERR 0
#define S_RXOVERSIZEERR 0
#define S_RXJABBERERR 0
#define S_RXUNDERSIZEFR 0
#define S_SQETESTERR 0
#define S_LENGTHERR 0
#define S_TXPAUSEFRAMES 0
#define S_MATCHHIGH 0
#define S_TYPEID 0
#define S_TXPAUSEQUANTUM 0
#define S_USERPROGOUTPUT 0
#define S_ARPIPADDR 0
#define S_DESREV 0
/* registers for module XGMAC */
#define S_PORT_SEL 0
#define S_HSS_RESET 0
#define S_LED0_POLARITY_INV 0
#define S_LED_COUNT_HI 0
#define S_LED_COUNT_LO 0
#define S_TESTCLK_SEL 0
#define S_AEC_PMA_RX_READY 0
#define S_RX_EOP_COUNT 0
#define S_MAC_WOL_DA 0
#define S_LINKDN 0
#define S_CHECKIN 0
#define S_FLTCTRL 0
#define S_SIGNALDETECT 0
#define S_CTRL 0
#define S_LWM 0
#define S_LASTOP 0
#define S_ADDRESS 0
#define S_MATCHEDFILTER 0
#define S_HSSPRBSEN 0
#define S_TXAPRBSEN 0
#define S_RXAPHSUPIN 0
#define S_HSSPRTREADY 0
#define S_XGM_TXEN 0
#define S_TXPAUSEEN 0
#define S_TXPAUSEQUANTA 0
#define S_COPYALLFRAMES 0
#define S_ADDRESS_HIGH 0
#define S_TYPE 0
#define S_FRAMERCVD 0
#define S_CURPAUSETIMER 0
#define S_ENTESTMODEWR 0
#define S_DATA 0
#define S_MODULEREV 0
#define S_TXBYTES_HIGH 0
#define S_TXFRAMES_HIGH 0
#define S_RXBYTES_HIGH 0
#define S_RXFRAMES_HIGH 0
#define S_RXPAUSEFRAMES 0
#define S_RXSHORTFRAMES 0
#define S_RXOVERSIZEFRAMES 0
#define S_RXJABBERFRAMES 0
#define S_RXCRCERRFRAMES 0
#define S_RXLENGTHERRFRAMES 0
#define G_RXLENGTHERRFRAMES(x) \
(((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
#define S_RXSYMCODEERRFRAMES 0
#define G_RXSYMCODEERRFRAMES(x) \
(((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
#define S_TEST_EN 0
#define S_LANE0_SYNC_STATUS 0
#define S_XGMIILOOPEN 0
#define S_TX_TST_EN 0
#define S_SEEDA_UPPER 0
#define S_SEEDB_UPPER 0
#define S_RX_TST_EN 0
#define S_TX_FAULT 0
#define S_TPT_ERR_CNT 0
#define S_PARTNER_AN_ABILITY 0
#define G_TRANSMITTED_NONCE(x) \
(((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
#define S_SELECTOR_FIELD 0
#define S_NP_INFO_HI 0
#define S_BP_AN_ABILITY 0
#define S_LFSR_INIT 0
#define S_PCS_AN_COMPLETE 0
#define S_GENERIC_TIMEOUT 0
#define S_BREAK_LINK_TIMEOUT 0
#define G_BREAK_LINK_TIMEOUT(x) \
(((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
#define S_MODULE_REVISION 0
#define S_RXREQ_C2 0
#define S_RXSTAT_C2 0
#define S_TXREQ_C2 0
#define S_TXSTAT_C2 0
#define S_STICKY_MODE 0
#define S_PRBS_GEN_OFF 0
#define S_FSM_TR_EN 0
#define S_TFSM_STATE 0
#define S_PMD_TX_DIS 0
#define S_RESTART_TRAINING 0
#define S_PMD_SIGDET 0
#define S_RX_TRAINED 0
#define S_RTSEL 0
#define S_TPSEL 0
#define S_ALOAD 0
#define S_FFE 0
#define S_IDAC 0
#define S_STBY 0
#define S_PON 0
#define S_NXTT0 0
#define S_NXTT1 0
#define S_NXTT2 0
#define S_TXPWR 0
#define S_NTXPOL 0
#define S_C0UPDT 0
#define S_C0STAT 0
#define S_NIDAC0 0
#define S_NIDAC1 0
#define S_NIDAC2 0
#define S_OPVAL 0
#define S_PDAC 0
#define S_AIDAC0 0
#define S_AIDAC1 0
#define S_TXA_AIDAC2 0
#define S_CURSD 0
#define S_XDATA 0
#define S_XWR 0
#define S_AIDAC2 0
#define S_PRBSSEL 0
#define S_SSCENABLE 0
#define S_PHOFFS 0
#define S_RTSEL_SNAPSHOT 0
#define S_ROT90 0
#define S_RDOFF 0
#define S_SDLVL 0
#define S_DFERST 0
#define S_DSAMP 0
#define S_ASAMP 0
#define S_VOFFA 0
#define S_VGAIN 0
#define S_AMAXT 0
#define S_D00AMP 0
#define S_D10AMP 0
#define S_E0AMP 0
#define S_AOFFE 0
#define S_DACAP 0
#define S_DACAM 0
#define S_ADMAG 0
#define S_MINAMP 0
#define S_EMEN 0
#define S_H1EMAG 0
#define S_H2EMAG 0
#define S_H3EMAG 0
#define S_H4EMAG 0
#define S_H5EMAG 0
#define S_OAE 0
#define S_ODEC 0
#define S_OCCMP 0
#define S_FADAC 0
#define S_BSELO 0
#define S_BSELI 0
#define S_TCDIS 0
#define S_CCLD 0
#define S_ATST 0
#define S_TXAEN 0
#define S_TXARST 0
#define S_CPISEL 0
#define S_BGCTL 0
#define S_LFSEL 0
#define S_VBADJ 0
/* registers for module UP */
#define S_IBQEN 0
#define S_OBQEN 0
#define S_IBQEMPTY 0
#define S_OBQFULL 0
#define S_IBQRDADDR 0
#define S_IBQWRADDR 0
#define S_QUEREMFLITS 0
#define S_QUESOPCNT 0
#define S_QUERDADDR 0
#define S_QUEWRADDR 0
#define S_QUEBAREADDR 0
#define S_MBPFINT 0
#define S_UPDBGLAEN 0
#define S_UPRID 0
#define S_UPSELFRESET 0
#define S_TSCHCHNLCWRDY 0
#define S_TSCHCHNLCWATCH 0
#define S_TSCHCHNLCCNT 0
/* registers for module CIM_CTL */
#define S_PREFEN 0
#define S_CTLFIFOCNT 0
#define S_GENTIMERSTRT 0
#define S_TSCHNLTICK 0
#define S_TSC0RATEEN 0
#define S_MIN_MAX_EN 0
#define S_TSCHNLRATEL 0
#define S_TSCHNLRINCR 0
#define S_TSCHNLWEIGHT 0
#define S_TSCCLRINCR 0
#define S_TSCCLWRR 0
#define S_TSCCLWEIGHT 0
#endif /* _CXGBE_T4_REGS_H */