80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * This file and its contents are supplied under the terms of the
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Common Development and Distribution License ("CDDL"), version 1.0.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * You may only use this file in accordance with the terms of version
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 1.0 of the CDDL.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * A full copy of the text of the CDDL should have accompanied this
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * source. A copy of the CDDL is also available via the Internet at
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Copyright (C) 2013 Hewlett-Packard Development Company, L.P.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Ioctl Commands
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_IOCTL_DRIVER_INFO CPQARY3_IOCTL_CMD | 0x01
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_IOCTL_CTLR_INFO CPQARY3_IOCTL_CMD | 0x02
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_IOCTL_BMIC_PASS CPQARY3_IOCTL_CMD | 0x04
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_IOCTL_SCSI_PASS CPQARY3_IOCTL_CMD | 0x08
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* Driver Revision : Used in Ioctl */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* Some Useful definations */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Defines for cleanup in cpqary3_attach and cpqary3_detach.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_HBA_TRAN_ALLOC_DONE 0x0001
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_HBA_TRAN_ATTACH_DONE 0x0002
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_SOFTSTATE_ALLOC_DONE 0x0020
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_TICKTMOUT_VALUE 180000000 /* 180 seconds */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Defines for Maximum and Default Settings.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MAX_LOGDRV 64 /* Max supported Logical Drivers */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MAX_CTLRS 8 /* Max supported Controllers */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * NOTE: When changing the below two entries, Max SG count in cpqary3_ciss.h
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * should also be changed.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MAX_PERF_SG_CNT 64 /* Maximum S/G in performant mode */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_SG_CNT 30 /* minimum S/G in simple mode */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_PERF_SG_CNT 31 /* minimum S/G for performant mode */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_MAX_TGT (MAX_LOGDRV + MAX_TAPE + 1)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * SCSI Capabilities Related IDs
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_CAP_WIDE_XFER_ENABLED 0x04
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_CAP_UNTAG_DRV_QING_ENABLED 0x40
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Defines for HBA
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Macros for Data Access
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* SCSI Addr to Per Controller */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define SA2CTLR(saddr) ((cpqary3_t *)((saddr)->a_hba_tran->tran_hba_private))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define SA2TGT(sa) (sa)->a_target /* SCSI Addr to Target ID */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define SD2TGT(sd) (sd)->sd_address.a_target /* SCSI Dev to Target ID */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define SD2LUN(sd) (sd)->sd_address.a_lun /* SCSI Dev to Lun */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define SD2SA(sd) ((sd)->sd_address) /* SCSI Dev to SCSI Addr */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* SCSI Dev to Per Controller */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ((cpqary3_t *)sd->sd_address.a_hba_tran->tran_hba_private)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define PKT2PVTPKT(sp) ((cpqary3_pkt_t *)((sp)->pkt_ha_private))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define PVTPKT2MEM(p) ((cpqary3_cmdpvt_t *)p->memp)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MEM2CMD(m) ((CommandList_t *)m->cmdlist_memaddr)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define SP2CMD(sp) MEM2CMD(PVTPKT2MEM(PKT2PVTPKT(sp)))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CTLR2MEMLISTP(ctlr) ((cpqary3_cmdmemlist_t *)ctlr->cmdmemlistp)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MEM2PVTPKT(m) ((cpqary3_pkt_t *)m->pvt_pkt)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MEM2DRVPVT(m) ((cpqary3_private_t *)m->driverdata)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ((cpqary3_cmdpvt_t *)(CTLR2MEMLISTP(ctlr)->pool[tag]))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_SWAP(val) ((val >> 8) | ((val & 0xff) << 8))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define RETURN_VOID_IF_NULL(x) if (NULL == x) return
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define RETURN_NULL_IF_NULL(x) if (NULL == x) return (NULL)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define RETURN_FAILURE_IF_NULL(x) if (NULL == x) return (CPQARY3_FAILURE)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Macros for memory allocation/deallocations
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MEM_ZALLOC(x) kmem_zalloc(x, KM_NOSLEEP)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define MEM_SFREE(x, y) if (x) kmem_free((void*)x, y)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Convenient macros for reading/writing Configuration table registers
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_get8((ctlr)->ct_handle, (uint8_t *)(regp))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_put8((ctlr)->ct_handle, (uint8_t *)(regp), (value))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_get16((ctlr)->ct_handle, (uint16_t *)(regp))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_put16((ctlr)->ct_handle, (uint16_t *)(regp), (value))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_get32((ctlr)->ct_handle, (uint32_t *)(regp))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_put32((ctlr)->ct_handle, (uint32_t *)(regp), (value))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_put32((ctlr)->cp_handle, (uint32_t *)(regp), (value))
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_BUFFER_ERROR_CLEAR 0x0 /* to be used with bioerror */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_DMA_NO_CALLBACK 0x0 /* to be used with DMA calls */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_DMA_ALLOC_HANDLE_DONE 0x01
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_SYNCCMD_SEND_WAITSIG (0x0001)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Include the driver specific relevant header files here.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Per Target Structure
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski uint32_t logical_id : 30; /* at most 64 : 63 drives + 1 CTLR */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski uint32_t type : 2; /* NONE, CTLR, LOGICAL DRIVE, TAPE */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Values for the type field in the Per Target Structure (above)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_TARGET_NONE 0 /* No Device */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_TARGET_CTLR 1 /* Controller */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_TARGET_LOG_VOL 2 /* Logical Volume */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define CPQARY3_TARGET_TAPE 3 /* SCSI Device - Tape */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Index into PCI Configuration Registers for Base Address Registers(BAR)
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Currently, only index for BAR 0 and BAR 1 are defined
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define INDEX_PCI_BASE0 1 /* offset 0x10 */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define INDEX_PCI_BASE1 2 /* offset 0x14 */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* Offset Values for IO interface from BAR 0 */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* Offset Values for IO interface from BAR 1 */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define INTR_DISABLE_5300_MASK 0x00000008l
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define OUTBOUND_LIST_5300_EXISTS 0x00000008l
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define OUTBOUND_LIST_5I_EXISTS 0x00000004l
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define INTR_SIMPLE_LOCKUP_MASK 0x0000000cl
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#define INTR_SIMPLE_5I_LOCKUP_MASK 0x0000000cl
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskitypedef struct cpqary3_per_controller CTLR;
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Per Controller Structure
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski /* System Dependent Entities */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski /* Controller Specific Information */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski /* Condition Variables used */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski kcondvar_t cv_ioctl_wait; /* Variable for ioctls */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * CPQary3 driver related entities related to :
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Hardware & Software Interrupts, Cookies & Mutex.
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Timeout Handler
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Driver Transport Layer/Structure
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Database for the per-controller Command Memory Pool
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Target List for the per-controller
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_iblock_cookie_t hw_iblock_cookie; /* cookie for h/w intr */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_iblock_cookie_t sw_iblock_cookie; /* cookie for s/w intr */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_softintr_t cpqary3_softintr_id; /* s/w intr identifier */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski timeout_id_t tick_tmout_id; /* timeout identifier */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski scsi_hba_tran_t *hba_tran; /* transport structure */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski cpqary3_cmdmemlist_t *cmdmemlistp; /* database - Memory Pool */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski cpqary3_tgt_t *cpqary3_tgtp[CPQARY3_MAX_TGT];
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * PCI Configuration Registers
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x10 Primary I2O Memory BAR - for Host Interface
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x14 Primary DRAM 1 BAR - for Transport Configuration Table
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Host Interface Registers
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Offset from Primary I2O Memory BAR
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x20 Inbound Doorbell - for interrupting controller
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x30 Outbound List Status - for signalling status of Reply Q
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x34 Outbound Interrupt Mask - for masking Interrupts to host
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x40 Host Inbound Queue - Request Q
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x44 Host Outbound Queue - reply Q
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Offset from Primary DRAM 1 BAR
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * 0x00 Configuration Table - for Controller Transport Layer
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski /* LOCKUP CODE */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski /* LOCKUP CODE */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Private Structure for Self Issued Commands
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* cmd_flags */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski * Driver Private Packet
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski ddi_dma_cookie_t cmd_dmacookies[MAX_PERF_SG_CNT];
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski /* Driver Revision */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski /* HBA Info */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski uint8_t num_of_tgts; /* No of Logical Drive */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski/* Driver function definitions */
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_read_conf_file(dev_info_t *, cpqary3_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_intr_onoff(cpqary3_t *, uint8_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_lockup_intr_onoff(cpqary3_t *, uint8_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiuint8_t cpqary3_disable_NOE_command(cpqary3_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiuint8_t cpqary3_send_NOE_command(cpqary3_t *, cpqary3_cmdpvt_t *, uint8_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiuint16_t cpqary3_init_ctlr_resource(cpqary3_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiint32_t cpqary3_ioctl_driver_info(uintptr_t, int);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiint32_t cpqary3_ioctl_ctlr_info(uintptr_t, cpqary3_t *, int);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiint32_t cpqary3_ioctl_bmic_pass(uintptr_t, cpqary3_t *, int);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiint32_t cpqary3_ioctl_scsi_pass(uintptr_t, cpqary3_t *, int);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiuint8_t cpqary3_probe4targets(cpqary3_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_cmdlist_release(cpqary3_cmdpvt_t *, uint8_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiint32_t cpqary3_submit(cpqary3_t *, uint32_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_free_phyctgs_mem(cpqary3_phyctg_t *, uint8_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskicaddr_t cpqary3_alloc_phyctgs_mem(cpqary3_t *, size_t, uint32_t *,
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskicpqary3_cmdpvt_t *cpqary3_cmdlist_occupy(cpqary3_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_synccmd_complete(cpqary3_cmdpvt_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_NOE_handler(cpqary3_cmdpvt_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_synccmd_cleanup(cpqary3_cmdpvt_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiint cpqary3_target_geometry(struct scsi_address *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiuint8_t cpqary3_send_abortcmd(cpqary3_t *, uint16_t, CommandList_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_memfini(cpqary3_t *, uint8_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_noe_complete(cpqary3_cmdpvt_t *cpqary3_cmdpvtp);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskicpqary3_cmdpvt_t *cpqary3_synccmd_alloc(cpqary3_t *, size_t);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskivoid cpqary3_synccmd_free(cpqary3_t *, cpqary3_cmdpvt_t *);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiint cpqary3_synccmd_send(cpqary3_t *, cpqary3_cmdpvt_t *, clock_t, int);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiuint8_t cpqary3_poll_retrieve(cpqary3_t *cpqary3p, uint32_t poll_tag);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowskiuint8_t cpqary3_build_cmdlist(cpqary3_cmdpvt_t *cpqary3_cmdpvtp, uint32_t tid);
80c94ecd7a524eb933a4bb221a9618b9dc490e76Keith M Wesolowski#endif /* _CPQARY3_H */