/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
*/
/*
* Copyright (C) 2013 Hewlett-Packard Development Company, L.P.
*/
#ifndef _CPQARY3_H
#define _CPQARY3_H
#include <cpqary3_ciss.h>
#include <cpqary3_bd.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* Ioctl Commands
*/
/* Driver Revision : Used in Ioctl */
#define CPQARY3_MINOR_REV_NO 00
/* Some Useful definations */
#define CPQARY3_FAILURE 0
#define CPQARY3_FALSE 0
/*
* Defines for cleanup in cpqary3_attach and cpqary3_detach.
*/
/*
* Defines for Maximum and Default Settings.
*/
/*
* NOTE: When changing the below two entries, Max SG count in cpqary3_ciss.h
* should also be changed.
*/
/* SG */
/* SG */
/*
* SCSI Capabilities Related IDs
*/
/*
* Defines for HBA
*/
#define CAP_CHG_NOT_ALLOWED 0
/*
* Macros for Data Access
*/
/* SCSI Addr to Per Controller */
/* SCSI Dev to Per Controller */
/* MACROS */
#define CPQARY3_MIN(x, y) (x < y ? x : y)
/*
* Macros for memory allocation/deallocations
*/
/*
*/
/* PERF */
/* PERF */
/*
* Include the driver specific relevant header files here.
*/
#include "cpqary3_ciss.h"
#include "cpqary3_q_mem.h"
#include "cpqary3_noe.h"
#include "cpqary3_scsi.h"
#include "cpqary3_ioctl.h"
/*
* Per Target Structure
*/
typedef struct cpqary3_target {
union {
struct {
struct {
} properties;
/*
* Values for the type field in the Per Target Structure (above)
*/
/*
* Index into PCI Configuration Registers for Base Address Registers(BAR)
* Currently, only index for BAR 0 and BAR 1 are defined
*/
/* Offset Values for IO interface from BAR 0 */
/* Offset Values for IO interface from BAR 1 */
/*
* Per Controller Structure
*/
typedef struct cpqary3_per_controller {
/* System Dependent Entities */
/* Controller Specific Information */
/* Condition Variables used */
/*
* CPQary3 driver related entities related to :
* Hardware & Software Interrupts, Cookies & Mutex.
* Timeout Handler
* Database for the per-controller Command Memory Pool
* Target List for the per-controller
*/
/*
* PCI Configuration Registers
* 0x10 Primary I2O Memory BAR - for Host Interface
* 0x14 Primary DRAM 1 BAR - for Transport Configuration Table
*
* Host Interface Registers
* Offset from Primary I2O Memory BAR
* 0x20 Inbound Doorbell - for interrupting controller
* 0x30 Outbound List Status - for signalling status of Reply Q
* 0x34 Outbound Interrupt Mask - for masking Interrupts to host
* 0x40 Host Inbound Queue - Request Q
* 0x44 Host Outbound Queue - reply Q
*
* Offset from Primary DRAM 1 BAR
* 0x00 Configuration Table - for Controller Transport Layer
*/
/* LOCKUP CODE */
/* LOCKUP CODE */
/* SG */
/* SG */
} cpqary3_t;
/*
* Private Structure for Self Issued Commands
*/
typedef struct cpqary3_driver_private {
void *sg;
/* cmd_flags */
/*
* Driver Private Packet
*/
typedef struct cpqary3_pkt {
/* SG */
/* SG */
#pragma pack(1)
typedef struct cpqary3_ioctlresp {
/* Driver Revision */
struct cpqary3_revision {
/* HBA Info */
struct cpqary3_ctlr {
} cpqary3_ctlr;
typedef struct cpqary3_ioctlreq {
#pragma pack()
/* Driver function definitions */
void cpqary3_init_hbatran(cpqary3_t *);
void cpqary3_tick_hdlr(void *);
void cpqary3_flush_cache(cpqary3_t *);
cpqary3_phyctg_t *);
void cpqary3_synccmd_complete(cpqary3_cmdpvt_t *);
void cpqary3_NOE_handler(cpqary3_cmdpvt_t *);
void cpqary3_synccmd_cleanup(cpqary3_cmdpvt_t *);
int cpqary3_target_geometry(struct scsi_address *);
#ifdef __cplusplus
}
#endif
#endif /* _CPQARY3_H */