/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 QLogic Corporation. All rights reserved.
* Use is subject to license terms.
*/
/*
*/
#ifndef _QLT_REGS_H
#define _QLT_REGS_H
#include <sys/stmf_defines.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* Register offsets
*/
/*
* Ctrl Status register definitions
*/
/*
* #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12
*/
/*
* INTR_CTRL register
*/
/*
* INTR_STATUS register
*/
/*
* RISC_STATUS register
*/
/*
* Mailbox command completion status.
*/
/*
* HCCR commands
*/
/*
*/
typedef struct qlt_nvram {
/* NVRAM header. */
/* Firmware Initialization Control Block. */
/*
* BIT 0 = Hard Assigned Loop ID
* BIT 1 = Enable Fairness
* BIT 2 = Enable Full-Duplex
* BIT 3 = Reserved
* BIT 4 = Target Mode Enable
* BIT 5 = Initiator Mode Disable
* BIT 6 = Reserved
* BIT 7 = Reserved
*
* BIT 8 = Reserved
* BIT 9 = Disable Initial LIP
* BIT 10 = Descending Loop ID Search
* BIT 11 = Previous Assigned Loop ID
* BIT 12 = Reserved
* BIT 13 = Full Login after LIP
* BIT 14 = Node Name Option
* BIT 15-31 = Reserved
*/
/*
* BIT 0 = Operation Mode bit 0
* BIT 1 = Operation Mode bit 1
* BIT 2 = Operation Mode bit 2
* BIT 3 = Operation Mode bit 3
* BIT 4 = Connection Options bit 0
* BIT 5 = Connection Options bit 1
* BIT 6 = Connection Options bit 2
* BIT 7 = Enable Non part on LIHA failure
*
* BIT 8 = Enable Class 2
* BIT 9 = Enable ACK0
* BIT 10 = Reserved
* BIT 11 = Enable FC-SP Security
* BIT 12 = FC Tape Enable
* BIT 13-31 = Reserved
*/
/*
* BIT 0 = Reserved
* BIT 1 = Soft ID only
* BIT 2 = Reserved
* BIT 3 = Reserved
* BIT 4 = FCP RSP Payload bit 0
* BIT 5 = FCP RSP Payload bit 1
* BIT 6 = Enable Rec Out-of-Order data frame handling
* BIT 7 = Disable Automatic PLOGI on Local Loop
*
* BIT 8 = Reserved
* BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
* offset handling
* BIT 10 = Reserved
* BIT 11 = Reserved
* BIT 12 = Reserved
* BIT 13 = Data Rate bit 0
* BIT 14 = Data Rate bit 1
* BIT 15 = Data Rate bit 2
* BIT 16 = 75-ohm Termination Select
* BIT 17-31 = Reserved
*/
/*
* Serial Link Control (offset 56)
* BIT 0 = control enable
* BIT 1-15 = Reserved
*/
/*
* Serial Link Control 1G (offset 58)
* BIT 0-7 = Reserved
*
* BIT 8-10 = output swing
* BIT 11-13 = output emphasis
* BIT 14-15 = Reserved
*/
/*
* Serial Link Control 2G (offset 60)
* BIT 0-7 = Reserved
*
* BIT 8-10 = output swing
* BIT 11-13 = output emphasis
* BIT 14-15 = Reserved
*/
/*
* Serial Link Control 4G (offset 62)
* BIT 0-7 = Reserved
*
* BIT 8-10 = output swing
* BIT 11-13 = output emphasis
* BIT 14-15 = Reserved
*/
/* Offset 64. */
/* Offset 96. */
/* PCIe table entries. */
/* Offset 160. */
/* Offset 192. */
/* Offset 224. */
/*
* BIT 0 = Enable spinup delay
* BIT 1 = Disable BIOS
* BIT 2 = Enable Memory Map BIOS
* BIT 3 = Enable Selectable Boot
* BIT 4 = Disable RISC code load
* BIT 5 = Disable serdes
* BIT 6 = Enable opt boot mode
* BIT 7 = Enable int mode BIOS
*
* BIT 8 =
* BIT 9 =
* BIT 10 = Enable lip full login
* BIT 11 = Enable target reset
* BIT 12 =
* BIT 13 = Default Node Name Option
* BIT 14 = Default valid
* BIT 15 = Enable alternate WWN
*
* BIT 16-31 =
*/
/*
* BIT 0 = Selective Login
* BIT 1 = Alt-Boot Enable
* BIT 2 = Reserved
* BIT 3 = Enable Boot Order List
* BIT 4 = Reserved
* BIT 5 = Enable Selective LUN
* BIT 6 = Reserved
* BIT 7-31 =
*/
/*
* FCode parameters word (offset 344)
*
* BIT 0 = Enable BIOS pathname
* BIT 1 = fcode qlc
* BIT 2 = fcode host
* BIT 3-7 =
*/
/* Offset 352. */
/* Offset 384. */
/* Offset 416. */
/* Offset 448. */
/* Offset 476. */
/* Offset 480. */
/* Offset 488. */
} qlt_nvram_t;
/* ISP81xx Extended Initialisation Control Block */
typedef struct qlt_ext_icb_81xx {
typedef struct qlt_nvram_81xx {
/* NVRAM header. */
/* Firmware Initialization Control Block. */
/*
* BIT 0 = Hard Assigned Loop ID
* BIT 1 = Enable Fairness
* BIT 2 = Enable Full-Duplex
* BIT 3 = Reserved
* BIT 4 = Target Mode Enable
* BIT 5 = Initiator Mode Disable
* BIT 6 = Reserved
* BIT 7 = Reserved
*
* BIT 8 = Reserved
* BIT 9 = Reserved
* BIT 10 = Reserved
* BIT 11 = Reserved
* BIT 12 = Reserved
* BIT 13 = Reserved
* BIT 14 = Node Name Option
* BIT 15-31 = Reserved
*/
/*
* BIT 0 = Operation Mode bit 0
* BIT 1 = Operation Mode bit 1
* BIT 2 = Operation Mode bit 2
* BIT 3 = Operation Mode bit 3
* BIT 4 = Reserved
* BIT 5 = Reserved
* BIT 6 = Reserved
* BIT 7 = Reserved
*
* BIT 8 = Enable Class 2
* BIT 9 = Enable ACK0
* BIT 10 = Reserved
* BIT 11 = Enable FC-SP Security
* BIT 12 = FC Tape Enable
* BIT 13 = Reserved
* BIT 14 = Target PRLI Control
* BIT 15-31 = Reserved
*/
/*
* BIT 0 = Reserved
* BIT 1 = Soft ID only
* BIT 2 = Reserved
* BIT 3 = Reserved
* BIT 4 = FCP RSP Payload bit 0
* BIT 5 = FCP RSP Payload bit 1
* BIT 6 = Enable Rec Out-of-Order data frame handling
* BIT 7 = Reserved
*
* BIT 8 = Reserved
* BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
* offset handling
* BIT 10 = Reserved
* BIT 11 = Reserved
* BIT 12 = Reserved
* BIT 13 = Reserved
* BIT 14 = Reserved
* BIT 15 = Reserved
* BIT 16 = Reserved
* BIT 17 = Enable Multiple FCFs
* BIT 18-20 = MAC Addressing Mode
* BIT 21-25 = Ethernet Data Rate
* BIT 26 = Enable Ethernet Header Receive ATIO_Q
* BIT 27 = Enable Ethernet Header Receive RSP_Q
* BIT 28-29 = SPMA Selection
* BIT 30-31 = Reserved
*/
/* Offset 56 (38h). */
/* Offset 64 (40h). */
/* Offset 70 (46h). */
/* Offset 96 (60h). */
/* Offset 112 (70h). */
/* Offset 128 (80h). */
/* Offset 192. */
/* Offset 224. */
/*
* BIT 0 = Selective Login
* BIT 1 = Alt-Boot Enable
* BIT 2 = Reserved
* BIT 3 = Enable Boot Order List
* BIT 4 = Reserved
* BIT 5 = Enable Selective LUN
* BIT 6 = Reserved
* BIT 7-31 =
*/
/*
* FCode parameters word (offset 344)
*
* BIT 0 = Enable BIOS pathname
* BIT 1 = fcode qlc
* BIT 2 = fcode host
* BIT 3-7 =
*/
/* Offset 352. */
/* Offset 384. */
/* Offset 416. */
/* Offset 480. */
/* Offset 496. */
#ifdef __cplusplus
}
#endif
#endif /* _QLT_REGS_H */