/*
* Copyright 1994-2005 The FreeBSD Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* THIS SOFTWARE IS PROVIDED BY THE FREEBSD PROJECT ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE FREEBSD PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation are
* those of the authors and should not be interpreted as representing official
* policies, either expressed or implied, of the FreeBSD Project.
*/
#pragma ident "%Z%%M% %I% %E% SMI" /* suni1x10gexp_regs.h */
#ifndef _SUNI1x10GEXP_REGS_H
#define _SUNI1x10GEXP_REGS_H
/*
** Space allocated for each Exact Match Filter
** There are 8 filter configurations
*/
#define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
/*
** Space allocated for VLAN-Id Filter
** There are 8 filter configurations
*/
#define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
/*
** Space allocated for each MSTAT Counter
*/
#define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
/******************************************************************************/
/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/
/******************************************************************************/
/* Refer to the Register Bit Masks bellow for the naming of each register and */
/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */
/******************************************************************************/
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)
#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
/*----------------------------------------*/
/******************************************************************************/
/* -- End register offset definitions -- */
/******************************************************************************/
/******************************************************************************/
/** SUNI-1x10GE-XP REGISTER BIT MASKS **/
/******************************************************************************/
/*----------------------------------------------------------------------------
* Register 0x0001: S/UNI-1x10GE-XP Product Revision
* Bit 3-0 REVISION
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
* Bit 2 XAUI_ARESETB
* Bit 1 PL4_ARESETB
* Bit 0 DRESETB
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
* Bit 11 PL4IO_OUTCLKSEL
* Bit 9 SYSPCSLB
* Bit 8 LINEPCSLB
* Bit 7 MSTAT_BYPASS
* Bit 6 RXXG_BYPASS
* Bit 5 TXXG_BYPASS
* Bit 4 SOP_PAD_EN
* Bit 1 LOS_INV
* Bit 0 OVERRIDE_LOS
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0004: S/UNI-1x10GE-XP Device Status
* Bit 9 TOP_SXRA_EXPIRED
* Bit 8 TOP_MDIO_BUSY
* Bit 7 TOP_DTRB
* Bit 6 TOP_EXPIRED
* Bit 5 TOP_PAUSED
* Bit 4 TOP_PL4_ID_DOOL
* Bit 3 TOP_PL4_IS_DOOL
* Bit 2 TOP_PL4_ID_ROOL
* Bit 1 TOP_PL4_IS_ROOL
* Bit 0 TOP_PL4_OUT_ROOL
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0005: Global Performance Update and Clock Monitors
* Bit 15 TIP
* Bit 8 XAUI_REF_CLKA
* Bit 7 RXLANE3CLKA
* Bit 6 RXLANE2CLKA
* Bit 5 RXLANE1CLKA
* Bit 4 RXLANE0CLKA
* Bit 3 CSUCLKA
* Bit 2 TDCLKA
* Bit 1 RSCLKA
* Bit 0 RDCLKA
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0006: MDIO Command
* Bit 4 MDIO_RDINC
* Bit 3 MDIO_RSTAT
* Bit 2 MDIO_LCTLD
* Bit 1 MDIO_LCTLA
* Bit 0 MDIO_SPRE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0007: MDIO Interrupt Enable
* Bit 0 MDIO_BUSY_EN
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0008: MDIO Interrupt Status
* Bit 0 MDIO_BUSYI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0009: MMD PHY Address
* Bit 12-8 MDIO_DEVADR
* Bit 4-0 MDIO_PRTADR
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0
/*----------------------------------------------------------------------------
* Register 0x000C: OAM Interface Control
* Bit 6 MDO_OD_ENB
* Bit 5 MDI_INV
* Bit 4 MDI_SEL
* Bit 3 RXOAMEN
* Bit 2 RXOAMCLKEN
* Bit 1 TXOAMEN
* Bit 0 TXOAMCLKEN
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
* Bit 15 TOP_PL4IO_INT
* Bit 14 TOP_IRAM_INT
* Bit 13 TOP_ERAM_INT
* Bit 12 TOP_XAUI_INT
* Bit 11 TOP_MSTAT_INT
* Bit 10 TOP_RXXG_INT
* Bit 9 TOP_TXXG_INT
* Bit 8 TOP_XRF_INT
* Bit 7 TOP_XTEF_INT
* Bit 6 TOP_MDIO_BUSY_INT
* Bit 5 TOP_RXOAM_INT
* Bit 4 TOP_TXOAM_INT
* Bit 3 TOP_IFLX_INT
* Bit 2 TOP_EFLX_INT
* Bit 1 TOP_PL4ODP_INT
* Bit 0 TOP_PL4IDU_INT
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x000E:PM3393 Global interrupt enable
* Bit 15 TOP_INTE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0010: XTEF Miscellaneous Control
* Bit 7 RF_VAL
* Bit 6 RF_OVERRIDE
* Bit 5 LF_VAL
* Bit 4 LF_OVERRIDE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0011: XRF Miscellaneous Control
* Bit 6-4 EN_IDLE_REP
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0100: SERDES 3125 Configuration Register 1
* Bit 10 RXEQB_3
* Bit 8 RXEQB_2
* Bit 6 RXEQB_1
* Bit 4 RXEQB_0
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0101: SERDES 3125 Configuration Register 2
* Bit 12 YSEL
* Bit 7 PRE_EMPH_3
* Bit 6 PRE_EMPH_2
* Bit 5 PRE_EMPH_1
* Bit 4 PRE_EMPH_0
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0102: SERDES 3125 Interrupt Enable Register
* Bit 3 LASIE
* Bit 2 SPLL_RAE
* Bit 1 MPLL_RAE
* Bit 0 PLL_LOCKE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0103: SERDES 3125 Interrupt Visibility Register
* Bit 3 LASIV
* Bit 2 SPLL_RAV
* Bit 1 MPLL_RAV
* Bit 0 PLL_LOCKV
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0104: SERDES 3125 Interrupt Status Register
* Bit 3 LASII
* Bit 2 SPLL_RAI
* Bit 1 MPLL_RAI
* Bit 0 PLL_LOCKI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x0107: SERDES 3125 Test Configuration
* Bit 12 DUALTX
* Bit 10 HC_1
* Bit 9 HC_0
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2040: RXXG Configuration 1
* Bit 15 RXXG_RXEN
* Bit 14 RXXG_ROCF
* Bit 13 RXXG_PAD_STRIP
* Bit 10 RXXG_PUREP
* Bit 9 RXXG_LONGP
* Bit 8 RXXG_PARF
* Bit 7 RXXG_FLCHK
* Bit 5 RXXG_PASS_CTRL
* Bit 3 RXXG_CRC_STRIP
* Bit 2-0 RXXG_MIFG
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x02041: RXXG Configuration 2
* Bit 7-0 RXXG_HDRSIZE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2042: RXXG Configuration 3
* Bit 15 RXXG_MIN_LERRE
* Bit 14 RXXG_MAX_LERRE
* Bit 12 RXXG_LINE_ERRE
* Bit 10 RXXG_RX_OVRE
* Bit 9 RXXG_ADR_FILTERE
* Bit 8 RXXG_ERR_FILTERE
* Bit 5 RXXG_PRMB_ERRE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2043: RXXG Interrupt
* Bit 15 RXXG_MIN_LERRI
* Bit 14 RXXG_MAX_LERRI
* Bit 12 RXXG_LINE_ERRI
* Bit 10 RXXG_RX_OVRI
* Bit 9 RXXG_ADR_FILTERI
* Bit 8 RXXG_ERR_FILTERI
* Bit 5 RXXG_PRMB_ERRE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2049: RXXG Receive FIFO Threshold
* Bit 2-0 RXXG_CUT_THRU
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0
/*----------------------------------------------------------------------------
* Register 0x2062H - 0x2069: RXXG Exact Match VID
* Bit 11-0 RXXG_VID_MATCH
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0
/*----------------------------------------------------------------------------
* Register 0x206EH - 0x206F: RXXG Address Filter Control
* Bit 3 RXXG_FORWARD_ENABLE
* Bit 2 RXXG_VLAN_ENABLE
* Bit 1 RXXG_SRC_ADDR
* Bit 0 RXXG_MATCH_ENABLE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2070: RXXG Address Filter Control 2
* Bit 1 RXXG_PMODE
* Bit 0 RXXG_MHASH_EN
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2081: XRF Control Register 2
* Bit 6 EN_PKT_GEN
* Bit 4-2 PATT
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2088: XRF Interrupt Enable
* Bit 12-9 LANE_HICERE
* Bit 8-5 HS_SD_LANEE
* Bit 4 ALIGN_STATUS_ERRE
* Bit 3-0 LANE_SYNC_STAT_ERRE
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0
/*----------------------------------------------------------------------------
* Register 0x2089: XRF Interrupt Status
* Bit 12-9 LANE_HICERI
* Bit 8-5 HS_SD_LANEI
* Bit 4 ALIGN_STATUS_ERRI
* Bit 3-0 LANE_SYNC_STAT_ERRI
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0
/*----------------------------------------------------------------------------
* Register 0x208A: XRF Error Status
* Bit 8-5 HS_SD_LANE
* Bit 4 ALIGN_STATUS_ERR
* Bit 3-0 LANE_SYNC_STAT_ERR
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x208B: XRF Diagnostic Interrupt Enable
* Bit 7-4 LANE_OVERRUNE
* Bit 3-0 LANE_UNDERRUNE
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0
/*----------------------------------------------------------------------------
* Register 0x208C: XRF Diagnostic Interrupt Status
* Bit 7-4 LANE_OVERRUNI
* Bit 3-0 LANE_UNDERRUNI
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0
/*----------------------------------------------------------------------------
* Register 0x20C0: RXOAM Configuration
* Bit 15 RXOAM_BUSY
* Bit 14-12 RXOAM_F2_SEL
* Bit 10-8 RXOAM_F1_SEL
* Bit 7-6 RXOAM_FILTER_CTRL
* Bit 5-0 RXOAM_PX_EN
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0
/*----------------------------------------------------------------------------
* Register 0x20C1,0x20C2: RXOAM Filter Configuration
* Bit 15-8 RXOAM_FX_MASK
* Bit 7-0 RXOAM_FX_VAL
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0
/*----------------------------------------------------------------------------
* Register 0x20C3: RXOAM Configuration Register 2
* Bit 13 RXOAM_REC_BYTE_VAL
* Bit 11-10 RXOAM_BYPASS_MODE
* Bit 5-0 RXOAM_PX_CLEAR
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0
/*----------------------------------------------------------------------------
* Register 0x20C4: RXOAM HEC Configuration
* Bit 15-8 RXOAM_COSET
* Bit 2 RXOAM_HEC_ERR_PKT
* Bit 0 RXOAM_HEC_EN
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x20C7: RXOAM Interrupt Enable
* Bit 10 RXOAM_FILTER_THRSHE
* Bit 9 RXOAM_OAM_ERRE
* Bit 8 RXOAM_HECE_THRSHE
* Bit 7 RXOAM_SOPE
* Bit 6 RXOAM_RFE
* Bit 5 RXOAM_LFE
* Bit 4 RXOAM_DV_ERRE
* Bit 3 RXOAM_DATA_INVALIDE
* Bit 2 RXOAM_FILTER_DROPE
* Bit 1 RXOAM_HECE
* Bit 0 RXOAM_OFLE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x20C8: RXOAM Interrupt Status
* Bit 10 RXOAM_FILTER_THRSHI
* Bit 9 RXOAM_OAM_ERRI
* Bit 8 RXOAM_HECE_THRSHI
* Bit 7 RXOAM_SOPI
* Bit 6 RXOAM_RFI
* Bit 5 RXOAM_LFI
* Bit 4 RXOAM_DV_ERRI
* Bit 3 RXOAM_DATA_INVALIDI
* Bit 2 RXOAM_FILTER_DROPI
* Bit 1 RXOAM_HECI
* Bit 0 RXOAM_OFLI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x20C9: RXOAM Status
* Bit 10 RXOAM_FILTER_THRSHV
* Bit 8 RXOAM_HECE_THRSHV
* Bit 6 RXOAM_RFV
* Bit 5 RXOAM_LFV
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2100: MSTAT Control
* Bit 2 MSTAT_WRITE
* Bit 1 MSTAT_CLEAR
* Bit 0 MSTAT_SNAP
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2109: MSTAT Counter Write Address
* Bit 5-0 MSTAT_WRITE_ADDRESS
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
/*----------------------------------------------------------------------------
* Register 0x2200: IFLX Global Configuration Register
* Bit 15 IFLX_IRCU_ENABLE
* Bit 14 IFLX_IDSWT_ENABLE
* Bit 13-0 IFLX_IFD_CNT
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0
/*----------------------------------------------------------------------------
* Register 0x2209: IFLX FIFO Overflow Enable
* Bit 0 IFLX_OVFE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x220A: IFLX FIFO Overflow Interrupt
* Bit 0 IFLX_OVFI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x220D: IFLX Indirect Channel Address
* Bit 15 IFLX_BUSY
* Bit 14 IFLX_RWB
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
* Bit 9-0 IFLX_LOLIM
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0
/*----------------------------------------------------------------------------
* Register 0x220F: IFLX Indirect Logical FIFO High Limit
* Bit 9-0 IFLX_HILIM
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0
/*----------------------------------------------------------------------------
* Bit 15 IFLX_FULL
* Bit 14 IFLX_AFULL
* Bit 13-0 IFLX_AFTH
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0
/*----------------------------------------------------------------------------
* Bit 15 IFLX_EMPTY
* Bit 14 IFLX_AEMPTY
* Bit 13-0 IFLX_AETH
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_IFLX_AETH 0
/*----------------------------------------------------------------------------
* Register 0x2240: PL4MOS Configuration Register
* Bit 3 PL4MOS_RE_INIT
* Bit 2 PL4MOS_EN
* Bit 1 PL4MOS_NO_STATUS
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2243: PL4MOS MaxBurst1 Register
* Bit 11-0 PL4MOS_MAX_BURST1
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0
/*----------------------------------------------------------------------------
* Register 0x2244: PL4MOS MaxBurst2 Register
* Bit 11-0 PL4MOS_MAX_BURST2
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0
/*----------------------------------------------------------------------------
* Register 0x2245: PL4MOS Transfer Size Register
* Bit 7-0 PL4MOS_MAX_TRANSFER
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0
/*----------------------------------------------------------------------------
* Register 0x2280: PL4ODP Configuration
* Bit 15-12 PL4ODP_REPEAT_T
* Bit 8 PL4ODP_SOP_RULE
* Bit 1 PL4ODP_EN_PORTS
* Bit 0 PL4ODP_EN_DFWD
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2282: PL4ODP Interrupt Mask
* Bit 0 PL4ODP_OUT_DISE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2283: PL4ODP Interrupt
* Bit 0 PL4ODP_OUT_DISI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2300: PL4IO Lock Detect Status
* Bit 15 PL4IO_OUT_ROOLV
* Bit 12 PL4IO_IS_ROOLV
* Bit 11 PL4IO_DIP2_ERRV
* Bit 8 PL4IO_ID_ROOLV
* Bit 4 PL4IO_IS_DOOLV
* Bit 0 PL4IO_ID_DOOLV
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2301: PL4IO Lock Detect Change
* Bit 15 PL4IO_OUT_ROOLI
* Bit 12 PL4IO_IS_ROOLI
* Bit 11 PL4IO_DIP2_ERRI
* Bit 8 PL4IO_ID_ROOLI
* Bit 4 PL4IO_IS_DOOLI
* Bit 0 PL4IO_ID_DOOLI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2302: PL4IO Lock Detect Mask
* Bit 15 PL4IO_OUT_ROOLE
* Bit 12 PL4IO_IS_ROOLE
* Bit 11 PL4IO_DIP2_ERRE
* Bit 8 PL4IO_ID_ROOLE
* Bit 4 PL4IO_IS_DOOLE
* Bit 0 PL4IO_ID_DOOLE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x2303: PL4IO Lock Detect Limits
* Bit 15-8 PL4IO_REF_LIMIT
* Bit 7-0 PL4IO_TRAN_LIMIT
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0
/*----------------------------------------------------------------------------
* Register 0x2304: PL4IO Calendar Repetitions
* Bit 15-8 PL4IO_IN_MUL
* Bit 7-0 PL4IO_OUT_MUL
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0
/*----------------------------------------------------------------------------
* Register 0x2305: PL4IO Configuration
* Bit 15 PL4IO_DIP2_ERR_CHK
* Bit 11 PL4IO_ODAT_DIS
* Bit 10 PL4IO_TRAIN_DIS
* Bit 9 PL4IO_OSTAT_DIS
* Bit 8 PL4IO_ISTAT_DIS
* Bit 7 PL4IO_NO_ISTAT
* Bit 6 PL4IO_STAT_OUTSEL
* Bit 5 PL4IO_INSEL
* Bit 4 PL4IO_DLSEL
* Bit 1-0 PL4IO_OUTSEL
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0
/*----------------------------------------------------------------------------
* Register 0x3040: TXXG Configuration Register 1
* Bit 15 TXXG_TXEN0
* Bit 13 TXXG_HOSTPAUSE
* Bit 12-7 TXXG_IPGT
* Bit 5 TXXG_32BIT_ALIGN
* Bit 4 TXXG_CRCEN
* Bit 3 TXXG_FCTX
* Bit 2 TXXG_FCRX
* Bit 1 TXXG_PADEN
* Bit 0 TXXG_SPRE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3041: TXXG Configuration Register 2
* Bit 7-0 TXXG_HDRSIZE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3042: TXXG Configuration Register 3
* Bit 15 TXXG_FIFO_ERRE
* Bit 14 TXXG_FIFO_UDRE
* Bit 13 TXXG_MAX_LERRE
* Bit 12 TXXG_MIN_LERRE
* Bit 11 TXXG_XFERE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3043: TXXG Interrupt
* Bit 15 TXXG_FIFO_ERRI
* Bit 14 TXXG_FIFO_UDRI
* Bit 13 TXXG_MAX_LERRI
* Bit 12 TXXG_MIN_LERRI
* Bit 11 TXXG_XFERI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3044: TXXG Status Register
* Bit 1 TXXG_TXACTIVE
* Bit 0 TXXG_PAUSED
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register
* Bit 7-0 TXXG_TX_MINFR
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0
/*----------------------------------------------------------------------------
* Register 0x3052: TXXG Pause Quantum Value Configuration Register
* Bit 7-0 TXXG_FC_PAUSE_QNTM
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0
/*----------------------------------------------------------------------------
* Register 0x3080: XTEF Control
* Bit 3-0 XTEF_FORCE_PARITY_ERR
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3084: XTEF Interrupt Event Register
* Bit 0 XTEF_LOST_SYNCI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3085: XTEF Interrupt Enable Register
* Bit 0 XTEF_LOST_SYNCE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3086: XTEF Visibility Register
* Bit 0 XTEF_LOST_SYNCV
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x30C0: TXOAM OAM Configuration
* Bit 15 TXOAM_HEC_EN
* Bit 14 TXOAM_EMPTYCODE_EN
* Bit 13 TXOAM_FORCE_IDLE
* Bit 12 TXOAM_IGNORE_IDLE
* Bit 11-6 TXOAM_PX_OVERWRITE
* Bit 5-0 TXOAM_PX_SEL
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0
/*----------------------------------------------------------------------------
* Register 0x30C1: TXOAM Mini-Packet Rate Configuration
* Bit 15 TXOAM_MINIDIS
* Bit 14 TXOAM_BUSY
* Bit 13 TXOAM_TRANS_EN
* Bit 10-0 TXOAM_MINIRATE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
* Bit 13-10 TXOAM_FTHRESH
* Bit 9-6 TXOAM_MINIPOST
* Bit 5-0 TXOAM_MINIPRE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x30C6: TXOAM Interrupt Enable
* Bit 2 TXOAM_SOP_ERRE
* Bit 1 TXOAM_OFLE
* Bit 0 TXOAM_ERRE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x30C7: TXOAM Interrupt Status
* Bit 2 TXOAM_SOP_ERRI
* Bit 1 TXOAM_OFLI
* Bit 0 TXOAM_ERRI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x30CF: TXOAM Coset
* Bit 7-0 TXOAM_COSET
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3200: EFLX Global Configuration
* Bit 15 EFLX_ERCU_EN
* Bit 7 EFLX_EN_EDSWT
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3201: EFLX ERCU Global Status
* Bit 13 EFLX_OVF_ERR
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3202: EFLX Indirect Channel Address
* Bit 15 EFLX_BUSY
* Bit 14 EFLX_RDWRB
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3203: EFLX Indirect Logical FIFO Low Limit
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0
/*----------------------------------------------------------------------------
* Register 0x3204: EFLX Indirect Logical FIFO High Limit
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0
/*----------------------------------------------------------------------------
* Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
* Bit 15 EFLX_FULL
* Bit 14 EFLX_AFULL
* Bit 13-0 EFLX_AFTH
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0
/*----------------------------------------------------------------------------
* Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
* Bit 15 EFLX_EMPTY
* Bit 14 EFLX_AEMPTY
* Bit 13-0 EFLX_AETH
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_EFLX_AETH 0
/*----------------------------------------------------------------------------
* Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
*----------------------------------------------------------------------------*/
#define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0
/*----------------------------------------------------------------------------
* Register 0x320C: EFLX FIFO Overflow Error Enable
* Bit 0 EFLX_OVFE
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x320D: EFLX FIFO Overflow Error Indication
* Bit 0 EFLX_OVFI
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3210: EFLX Channel Provision
* Bit 0 EFLX_PROV
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3280: PL4IDU Configuration
* Bit 2 PL4IDU_SYNCH_ON_TRAIN
* Bit 1 PL4IDU_EN_PORTS
* Bit 0 PL4IDU_EN_DFWD
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3282: PL4IDU Interrupt Mask
* Bit 1 PL4IDU_DIP4E
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
* Register 0x3283: PL4IDU Interrupt
* Bit 1 PL4IDU_DIP4I
*----------------------------------------------------------------------------*/
#endif /* _SUNI1x10GEXP_REGS_H */