/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/* This file is automatically generated --- do not edit */
#pragma ident "%Z%%M% %I% %E% SMI" /* regs.h */
/* SGE registers */
#define S_CMDQ0_ENABLE 0
#define S_CMDQ0_SIZE 0
#define S_FL0_SIZE 0
#define S_RESPQ_SIZE 0
#define S_FL_THRESHOLD 0
#define S_RESPQ_CREDIT 0
#define S_SLEEPING 0
#define S_INTERRUPT_TIMER_COUNT 0
#define S_CMDQ0_POINTER 0
#define S_CMDQ1_POINTER 0
#define S_FL0_POINTER 0
#define S_FL1_POINTER 0
#define S_DAY 0
#define S_CMDQ1_SIZE 0
#define S_FL1_SIZE 0
#define S_RESPQ_EXHAUSTED 0
/* MC3 registers */
#define S_CLK_ENABLE 0
#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
#define S_MC3_MODE 0
#define S_MC3_EXTENDED_MODE 0
#define S_REFRESH_ENABLE 0
#define S_MASTER_DLL_RESET 0
#define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
#define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
#define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
#define S_ECC_GENERATION_ENABLE 0
#define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
#define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
#define S_BACK_DOOR_OPERATION 0
#define S_OP 0
#define S_MC3_CORR_ERR 0
/* MC4 registers */
#define S_POWER_UP 0
#define S_MC4_MODE 0
#define S_MC4_EXTENDED_MODE 0
#define S_MC4_BACK_DOOR_ADDR 0
#define S_OPERATION 0
#define S_MC4_CORR_ERR 0
/* TPI registers */
#define S_TPI_ADDRESS 0
#define S_TPIWR 0
#define S_TPIPAR 0
/* TP registers */
#define S_TP_IN_CSPI_TUNNEL 0
#define S_TP_OUT_C_ETH 0
#define S_IP_TTL 0
#define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
#define S_CM_MEMMGR_BASE 0
#define S_CM_TIMER_BASE 0
#define S_TIMESTAMP 0
#define S_DACK_MODE 0
#define S_TP_ACCESS_LATENCY 0
#define S_ELEMENT0 0
#define S_VAR_MULT 0
#define S_INITIAL_SLOW_START_THRESHOLD 0
#define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
#define S_RX_COALESCE_SIZE 0
#define S_RX_COALESCING_PSH_DELIVER 0
#define S_DELAYED_ACK_TIMER_RESOLUTION 0
#define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
#define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
#define S_2MSL 0
#define S_RETRANSMIT_TIMER_MIN 0
#define S_RETRANSMIT_TIMER_MAX 0
#define S_PERSIST_TIMER_MIN 0
#define S_PERSIST_TIMER_MAX 0
#define S_KEEP_ALIVE_IDLE_TIME 0
#define S_KEEP_ALIVE_INTERVAL_TIME 0
#define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
#define S_INITIAL_SRTT 0
#define S_DELAYED_ACK_TIME 0
#define S_FINWAIT2_TIME 0
#define S_FAST_FINWAIT2_TIME 0
#define S_KEEPALIVE_MAX 0
#define S_L3_VALUE 0
#define S_TP_RESET 0
#define S_CM_MEMMGR_RX_FREE_LIST_BASE 0
#define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
#define S_CM_MEMMGR_TX_FREE_LIST_BASE 0
#define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
#define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0
#define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
#define S_CM_MEMMGR_MAX_PSTRUCT 0
#define S_TX_FREE_LIST_EMPTY 0
#define S_DISABLE_PAST_TIMER_INSERTION 0
#define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
#define S_NUM_PKTS_DROPPED 0
/* RAT registers */
#define S_USE_ROUTE_TABLE 0
#define S_ROUTE_TABLE_INDEX 0
#define S_CPL_OPCODE 0
#define S_ZEROROUTEERROR 0
/* CSPI registers */
#define S_CALENDARLENGTH 0
#define S_FIFOSTATUSENABLE 0
#define S_MAXBURST1 0
#define S_CSPI_TRAIN_ALPHA 0
#define S_DIP4ERR 0
/* ESPI registers */
#define S_SCHTOKEN0 0
#define S_SCHTOKEN1 0
#define S_SCHTOKEN2 0
#define S_SCHTOKEN3 0
#define S_ALMOSTEMPTY 0
#define S_ALMOSTFULL 0
#define S_RX_NPORTS 0
#define S_RXSTATUSENABLE 0
#define S_MAXTRAINALPHA 0
#define S_RXFIFOPARITYERROR 0
#define S_TXPORT0DROPCNT 0
#define S_TXPORT2DROPCNT 0
#define S_RXPORT0DROPCNT 0
#define S_RXPORT2DROPCNT 0
#define S_DIP4ERRORCNT 0
#define S_ESPI_RX_LNK_RST 0
#define S_OUT_OF_SYNC_COUNT 0
#define S_DIP2_ERR_CNT 0
#define S_WRITE_DATA 0
#define S_READ_DATA 0
/* ULP registers */
#define S_HREG_PAR_ERR 0
/* PL registers */
#define S_PL_INTR_SGE_ERR 0
/* MC5 registers */
#define S_MODE 0
#define S_SIZE 0
#define S_START_OF_ROUTING_TABLE 0
#define S_START_OF_SERVER_INDEX 0
#define S_LOCAL_IP_RAM_ADDR 0
#define S_SEARCH_RESPONSE_LATENCY 0
#define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)
#define S_SRCHLAT 0
#define S_POVEREN 0
#define S_IDINDEX 0
#define S_RSTMAX 0
#define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0
#define S_CMDMODE 0
#define S_DBGI_RSP_VALID 0
/* PCICFG registers */
#define S_VPD_ADDR 0
#define S_MASTER_PARITY_ERR 0
#define S_PCI_MODE_64BIT 0