d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Update fast changing statistics every 15 seconds */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* 30 minutes for full statistics update */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The IXF1010 can handle frames up to 16383 bytes but it's optimized for
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * frames up to 9831 (0x2667) bytes, so we limit jumbo frame size to this.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * This length includes ethernet header and FCS.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* MAC registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Per-port registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Global registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwenum { /* RMON registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MACREG(mac, mac_reg) ((mac)->instance->mac_base + (mac_reg))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read((mac)->adapter, MACREG(mac, REG_##name), &val); \
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Read the current values of the RMON counters and add them to the cumulative
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * port statistics. The HW RMON counters are cleared by this operation.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Rx stats */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw RMON_UPDATE(mac, RxVeryLongErrors, RxFrameTooLongErrors);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw RMON_UPDATE(mac, RxPauseMacControlCounter, RxPauseFrames);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* Tx stats (skip collision stats as we are full-duplex only) */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* No-op interrupt operation as this MAC does not support interrupts */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* ARGSUSED */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* Expect MAC address to be in network byte order. */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_LOW), addr_lo);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), addr_hi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_LOW), &addr_lo);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), &addr_hi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* This is intended to reset a port, not the whole MAC */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* ARGSUSED */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(adapter, MACREG(mac, REG_RX_FILTER), &val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (!t1_rx_mode_promisc(rm) && mac->instance->version > 0)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw new_mode |= 1; /* only set if version > 0 due to erratum */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), new_mode);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), 0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw addr_lo = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), addr_lo);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), addr_hi);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* MAX_FRAME_SIZE inludes header + FCS, mtu doesn't */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MAX_FRAME_SIZE),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (speed >= 0 && speed != SPEED_100 && speed != SPEED_1000)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return -1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw return -1;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw if (speed >= 0) {
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_RGMII_SPEED), val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_FC_ENABLE), val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic int mac_get_speed_duplex_fc(struct cmac *mac, int *speed, int *duplex,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_RGMII_SPEED),
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_read(adapter, MACREG(mac, REG_DIVERSE_CONFIG), &val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw val |= DIVERSE_CONFIG_CRC_ADD | DIVERSE_CONFIG_PAD_ENABLE;
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_DIVERSE_CONFIG), val);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 3);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw else /* Don't enable unicast address filtering due to IXF1010 bug */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 2);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Clear the port RMON registers by adding their current values to the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * cumulatice port stats and then clearing the stats. Really.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) memset(&mac->stats, 0, sizeof(struct cmac_statistics));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw /* T204: set the Fifo water level & threshold */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, RX_FIFO_HIGH_WATERMARK_BASE + index, 0x740);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, RX_FIFO_LOW_WATERMARK_BASE + index, 0x730);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, TX_FIFO_HIGH_WATERMARK_BASE + index, 0x600);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, TX_FIFO_LOW_WATERMARK_BASE + index, 0x1d0);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw (void) t1_tpi_write(adapter, TX_FIFO_XFER_THRES_BASE + index, 0x1100);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Set the TX Fifo Threshold to 0x400 instead of 0x100 to work around
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Underrun problem. Intel has blessed this solution.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw TX_FIFO_XFER_THRES_BASE + mac->instance->index * 4, 0x400);
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* IXF1010 ports do not have separate enables for TX and RX */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * This function is called periodically to accumulate the current values of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * RMON counters into the port statistics. Since the counters are only 32 bits
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * some of them can overflow in less than a minute at GigE speeds, so this
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * function should be called every 30 seconds or so.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * To cut down on reading costs we update only the octet counters at each tick
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and do a full update at major ticks, which can be every 30 minutes or more.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw t1_os_free((void *)mac, sizeof(*mac) + sizeof(cmac_instance));
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xwstatic struct cmac *ixf1010_mac_create(adapter_t *adapter, int index)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw mac = t1_os_malloc_wait_zero(sizeof(*mac) + sizeof(cmac_instance));