/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
*/
#pragma ident "%Z%%M% %I% %E% SMI" /* ixf1010.c */
#include "gmac.h"
#include "elmer0.h"
/* Update fast changing statistics every 15 seconds */
/* 30 minutes for full statistics update */
/*
* The IXF1010 can handle frames up to 16383 bytes but it's optimized for
* frames up to 9831 (0x2667) bytes, so we limit jumbo frame size to this.
* This length includes ethernet header and FCS.
*/
/* MAC registers */
enum {
/* Per-port registers */
REG_MACADDR_LOW = 0,
/* Global registers */
};
enum { /* RMON registers */
};
enum {
};
#define MACREG_BASE 0
struct _cmac_instance {
};
{
}
/*
* Read the current values of the RMON counters and add them to the cumulative
* port statistics. The HW RMON counters are cleared by this operation.
*/
{
/* Rx stats */
/* Tx stats (skip collision stats as we are full-duplex only) */
}
/* No-op interrupt operation as this MAC does not support interrupts */
/* ARGSUSED */
{
return 0;
}
/* Expect MAC address to be in network byte order. */
{
return 0;
}
{
return 0;
}
/* This is intended to reset a port, not the whole MAC */
/* ARGSUSED */
{
return 0;
}
{
new_mode |= 2;
switch (t1_rx_mode_mc_cnt(rm)) {
case 0:
break;
case 1:
addr[5];
break;
default:
break;
}
return 0;
}
{
/* MAX_FRAME_SIZE inludes header + FCS, mtu doesn't */
return 0;
}
int fc)
{
return -1;
return -1;
if (speed >= 0) {
}
val &= ~3;
val |= 1;
val |= 2;
return 0;
}
int *fc)
{
if (duplex)
*duplex = DUPLEX_FULL;
if (speed) {
&val);
}
if (fc) {
*fc = 0;
if (val & 1)
if (val & 2)
}
return 0;
}
{
else /* Don't enable unicast address filtering due to IXF1010 bug */
/*
* Clear the port RMON registers by adding their current values to the
* cumulatice port stats and then clearing the stats. Really.
*/
index <<= 2;
/* T204: set the Fifo water level & threshold */
} else {
/*
* Set the TX Fifo Threshold to 0x400 instead of 0x100 to work around
* Underrun problem. Intel has blessed this solution.
*/
(void) t1_tpi_write(adapter,
}
}
/* IXF1010 ports do not have separate enables for TX and RX */
{
return 0;
}
{
return 0;
}
/*
* This function is called periodically to accumulate the current values of the
* RMON counters into the port statistics. Since the counters are only 32 bits
* some of them can overflow in less than a minute at GigE speeds, so this
* function should be called every 30 seconds or so.
*
* To cut down on reading costs we update only the octet counters at each tick
* and do a full update at major ticks, which can be every 30 minutes or more.
*/
int flag)
{
if (flag == MAC_STATS_UPDATE_FULL ||
} else {
}
}
{
}
#ifdef C99_NOT_SUPPORTED
NULL,
NULL,
NULL,
};
#else
.destroy = mac_destroy,
.enable = mac_enable,
.disable = mac_disable,
.set_mtu = mac_set_mtu,
};
#endif
{
if ((val & 1) != 0) {
val &= ~1;
DELAY_US(2);
}
val |= 1;
DELAY_US(2);
return 0;
}
{
return mac;
}
};