d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA specific definitions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* FPGA master interrupt Cause/Enable bits */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* TP interrupt register addresses */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* TP interrupt Cause/Enable bits */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * PM interrupt register addresses
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * GMAC interrupt register addresses
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* GMAC Cause/Enable bits */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* MI0 registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* GMAC registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)