d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER START
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * The contents of this file are subject to the terms of the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Common Development and Distribution License (the "License").
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You may not use this file except in compliance with the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * or http://www.opensolaris.org/os/licensing.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * See the License for the specific language governing permissions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * and limitations under the License.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * When distributing Covered Code, include this CDDL HEADER in each
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * If applicable, add the following below this CDDL HEADER, with the
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * fields enclosed by brackets "[]" replaced with your own identifying
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * information: Portions Copyright [yyyy] [name of copyright owner]
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw *
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * CDDL HEADER END
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * FPGA specific definitions
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#pragma ident "%Z%%M% %I% %E% SMI" /* fpga_defs.h */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#ifndef __CHELSIO_FPGA_DEFS_H__
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define __CHELSIO_FPGA_DEFS_H__
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_ADDR_VERSION 0xA08
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_ADDR_STAT 0xA0C
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* FPGA master interrupt Cause/Enable bits */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_INTERRUPT_TP 0x4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_INTERRUPT_MC3 0x8
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_INTERRUPT_GMAC 0x10
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_PCIX_INTERRUPT_PCIX 0x20
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* TP interrupt register addresses */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_TP_ADDR_VERSION 0xA18
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* TP interrupt Cause/Enable bits */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_TP_INTERRUPT_MC4 0x1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_TP_INTERRUPT_MC5 0x2
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * PM interrupt register addresses
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_MC3_REG_INTRENABLE 0xA20
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_MC3_REG_INTRCAUSE 0xA24
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_MC3_REG_VERSION 0xA28
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/*
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw * GMAC interrupt register addresses
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_GMAC_ADDR_VERSION 0xA38
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* GMAC Cause/Enable bits */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_GMAC_INTERRUPT_PORT0 0x1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_GMAC_INTERRUPT_PORT1 0x2
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_GMAC_INTERRUPT_PORT2 0x4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define FPGA_GMAC_INTERRUPT_PORT3 0x8
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* MI0 registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_MI0_CLK 0xb00
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_CLK_DIV 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_MI0_CLK_DIV 0xff
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_CLK_CNT 8
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_MI0_CLK_CNT 0xff
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_MI0_CSR 0xb04
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_CSR_POLL 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_PREAMBLE 1
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_INTR_ENABLE 2
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_BUSY 3
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MI0_BUSY V_MI0_BUSY(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_MDIO 4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MI0_MDIO V_MI0_MDIO(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_MI0_ADDR 0xb08
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_PHY_REG_ADDR 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_MI0_PHY_REG_ADDR 0x1f
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MI0_PHY_ADDR 5
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_MI0_PHY_ADDR 0x1f
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_MI0_DATA_EXT 0xb0c
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_MI0_DATA_INT 0xb10
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw/* GMAC registers */
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_MACID_LO 0x28
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_MACID_HI 0x2c
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_CSR 0x30
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_INTERFACE 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_INTERFACE 0x3
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_INTERFACE(x) ((x) << S_INTERFACE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_TX_ENABLE 2
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_RX_ENABLE 3
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_LB_ENABLE 4
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_SPEED 5
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_MAC_SPEED 0x3
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_HD_FC_ENABLE 7
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_HALF_DUPLEX 8
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_PROMISC 9
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_PROMISC V_MAC_PROMISC(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_MC_ENABLE 10
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_RESET 11
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RESET(x) ((x) << S_MAC_RESET)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_RESET V_MAC_RESET(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_RX_PAUSE_ENABLE 12
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_TX_PAUSE_ENABLE 13
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_LWM_ENABLE 14
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_MAGIC_PKT_ENABLE 15
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_ISL_ENABLE 16
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_JUMBO_ENABLE 17
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_RX_PAD_ENABLE 18
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_RX_CRC_ENABLE 19
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_IFS 0x34
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_IFS2 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_MAC_IFS2 0x3f
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_MAC_IFS1 8
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_MAC_IFS1 0x7f
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_JUMBO_FRAME_LEN 0x38
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_LNK_DLY 0x3c
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_PAUSETIME 0x40
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_MCAST_LO 0x44
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_MCAST_HI 0x48
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_MCAST_MASK_LO 0x4c
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_MCAST_MASK_HI 0x50
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_RMT_CNT 0x54
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_RMT_DATA 0x58
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_BACKOFF_SEED 0x5c
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define A_GMAC_TXF_THRES 0x60
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_TXF_READ_THRESHOLD 0
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_TXF_READ_THRESHOLD 0xff
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define S_TXF_WRITE_THRESHOLD 16
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define M_TXF_WRITE_THRESHOLD 0xff
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_BASE 0x600
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw
d39a76e7b087a3d0927cbe6898dc0a6770fa6c68xw#endif