/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
*/
/*
* FPGA specific definitions
*/
#pragma ident "%Z%%M% %I% %E% SMI" /* fpga_defs.h */
#ifndef __CHELSIO_FPGA_DEFS_H__
#define __CHELSIO_FPGA_DEFS_H__
/* TP interrupt register addresses */
/*
* PM interrupt register addresses
*/
/*
* GMAC interrupt register addresses
*/
/* MI0 registers */
#define S_MI0_CLK_DIV 0
#define S_MI0_CSR_POLL 0
#define S_MI0_PHY_REG_ADDR 0
/* GMAC registers */
#define S_INTERFACE 0
#define S_MAC_IFS2 0
#define S_TXF_READ_THRESHOLD 0
#endif